XQV100 Datasheet, PDF (27/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

R
Pinout Diagrams
The following diagrams illustrate the locations of spe-
cial-purpose pins on Virtex FPGAs. Table 6 lists the sym-
bols used in these diagrams. The diagrams also show
I/O-bank boundaries.
Table 6: Pinout Diagram Symbols
Symbol Pin Function
S
General I/O
d
Device-dependent general I/O, n/c on
smaller devices
V
V_CCINT
v
Device-dependent V_CCINT, n/c on smaller
devices
O
V_CCO
R
V_REF
r
Device-dependent V_REF, remains I/O on
smaller devices
G
Ground
Ø, 1, 2, 3 Global Clocks
QPro Virtex 2.5V QML High-Reliability FPGAs
Table 6: Pinout Diagram Symbols
Symbol Pin Function
❿, ❶, ❷ M0, M1, M2
➉, ➀, ➁, ➂, D0/DIN, D1, D2, D3, D4, D5, D6, D7
➃, ➄, ➅, ➆
B
DOUT/BUSY
D
DONE
P
PROGRAM
I
INIT
K
CCLK
W
WRITE
S
CS
T
Boundary-scan test aAccess port
+
Temperature diode, anode
–
Temperature diode, cathode
n
No connect
DS002 (v1.5) December 5, 2001
www.xilinx.com
27
Preliminary Product Specification
1-800-255-7778