XQV100 Datasheet, PDF (7/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

R
QPro Virtex 2.5V QML High-Reliability FPGAs
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in "IOB Output Switching Characteristics Standard Adjustments" on page 8.
Speed Grade
-4
Symbol
Description
Min Max Units
Propagation Delays
T_IOOP
T_IOOLP
3-State Delays
O input to pad
O input to pad via transparent latch
-
3.5
ns
-
4.0
ns
T_IOTHZ
T_IOTON
T_IOTLPHZ
T_IOTLPON
T_GTS
Sequential Delays
T input to pad high-impedance⁽¹⁾
T input to valid data on pad
T input to pad high-impedance via transparent latch⁽¹⁾
T input to valid data on pad via transparent latch
GTS to pad high-impedance⁽¹⁾
-
2.4
ns
-
3.7
ns
-
3.0
ns
-
4.2
ns
-
6.3
ns
T_IOCKP
T_IOCKHZ
Clock CLK to pad
Clock CLK to pad high-impedance (synchronous)⁽¹⁾
T_IOCKON
Clock CLK to valid data on pad (synchronous)
Setup and Hold Times before/after Clock CLK
-
3.5
ns
-
2.9
ns
-
4.1
ns
Setup Time / Hold Time⁽²⁾
T_IOOCK/T_IOCKO
T_IOOCECK/T_IOCKOCE
T_IOSRCKO/T_IOCKOSR
T_IOTCK/T_IOCKT
T_IOTCECK/T_IOCKTCE
T_IOSRCKT/T_IOCKTSR
Set/Reset Delays
O input
OCE input
SR input (OFF)
3-state setup times, T input
3-state setup times, TCE input
3-state setup times, SR input (TFF)
1.3 / 0
-
ns
1.0 / 0
-
ns
1.4 / 0
-
ns
0.9 / 0
-
ns
1.1 / 0
-
ns
1.3 / 0
-
ns
T_IOSRP
T_IOSRHZ
SR input to pad (asynchronous)
SR input to pad high-impedance (asynchronous)⁽¹⁾
4.6
-
ns
3.9
-
ns
T_IOSRON
SR input to valid data on pad (asynchronous)
5.1
-
ns
Notes:
1. High-impedance turn-off delays should not be adjusted.
2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS002 (v1.5) December 5, 2001
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Preliminary Product Specification
1-800-255-7778