XQV100 Datasheet, PDF (16/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

QPro Virtex 2.5V QML High-Reliability FPGAs
R
DLL Timing Parameters
Switching parameters testing is modeled after testing meth-
ods specified by MIL-M-38510/605; all devices are 100 per-
cent functionally tested. Because of the difficulty in directly
measuring many internal timing parameters, those parame-
ters are derived from benchmark timing patterns. The fol-
lowing guidelines reflect worst-case values across the
recommended operating conditions.
Symbol
Description
F_CLKINHF
Input clock frequency (CLKDLLHF)
F_CLKINLF
Inputclock frequency (CLKDLL)
T_DLLPWHF
Input clock pulse width (CLKDLLHF)
T_DLLPWLF
Input clock pulse width (CLKDLL)
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
Speed Grade -4
Min
Max
60
180
25
90
2.4
-
3.0
-
Units
MHz
MHz
ns
ns
CLKDLLHF
Symbol
Description
Min
Max
T_IPTOL
T_IJITCC
T_LOCK
Input clock period tolerance
Input clock jitter cycle to cycle
Time required for DLL to acquire Lock
F_CLKIN
-
1.0
-
±150
> 60 MHz
-
20
50-60 MHz
-
-
40-50 MHz
-
-
30-40 MHz
-
-
25-30 MHz
-
-
T_SKEW DLL output skew (between any DLL output)
-
T_OPHASE DLL output long term phase differential
-
T_OJITCC DLL output ditter cycle to cycle
-
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
±150
±100
±60
CLKDLL
Min
Max
-
1.0
-
±300
Units
ns
ps
-
20
µs
-
25
µs
-
50
µs
-
90
µs
-
120
µs
-
±150
ps
-
±100
ps
-
±60
ps
Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN
TCLKIN +_ TIPTOL
Clock Jitter: the difference between an ideal reference clock edgfe and the actual design.
_+
TOJITCC
Figure 1: Frequency Tolerance and Clock Jitter
DS002_01_060100
16
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DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification