XQV100 Datasheet, PDF (10/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

QPro Virtex 2.5V QML High-Reliability FPGAs
R
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Speed Grade
-4
Symbol
Description
Min Max Units
Combinatorial Delays
T_ILO
4-input function: F/G inputs to X/Y outputs
-
0.8
ns
T_IF5
5-input function: F/G inputs to F5 output
-
0.9
ns
T_IF5X
5-input function: F/G inputs to X output
-
1.0
ns
T_IF6Y
6-input function: F/G inputs to Y output via F6 MUX
-
1.2
ns
T_F5INY
6-input function: F5IN input to Y output
-
0.5
ns
T_IFNCTL
Incremental delay routing through transparent latch to XQ/YQ outputs
-
0.8
ns
T_BYYB
BY input to YB output
-
0.7
ns
Sequential Delays
T_CKO
FF clock CLK to XQ/YQ outputs
T_CKLO
Latch clock CLK to XQ/YQ outputs
Setup and Hold Times before/after Clock CLK
-
1.4
ns
-
1.6
ns
Setup Time / Hold Time
T_ICK/T_CKI
T_IF5CK/T_CKIF5
T_F5INCK/T_CKF5IN
T_IF6CK/T_CKIF6
T_DICK/T_CKDI
T_CECK/T_CKCE
T_RCKT_CKR
Clock CLK
4-input function: F/G Inputs
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
CE input
SR/BY inputs (synchronous)
1.5 / 0 -
ns
1.7 / 0 -
ns
1.2 / 0 -
ns
1.9 / 0 -
ns
0.8 / 0 -
ns
1.0 / 0 -
ns
0.9 / 0 -
ns
T_CH
T_CL
Set/Reset
Minimum pulse width, High
Minimum pulse width, Low
2.0
-
ns
2.0
-
ns
T_RPW
Minimum pulse width, SR/BY inputs
3.3
-
ns
T_RQ
Delay from SR/BY inputs to XQ/YQ outputs (asynchronous)
-
1.4
ns
T_IOGSRQ
Delay from GSR to XQ/YQ outputs
-
12.5
ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
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DS002 (v1.5) December 5, 2001
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Preliminary Product Specification