XQV100 Datasheet, PDF (5/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

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QPro Virtex 2.5V QML High-Reliability FPGAs
Virtex Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Virtex devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in "IOB Input Switching Characteristics
Standard Adjustments" on page 6.
Speed Grade
-4
Symbol
Description
Device
Min Max Units
Propagation Delays
T_IOPI
T_IOPID
Pad to I output, no delay
Pad to I output, with delay
All
-
1.0
ns
XQV100
-
1.9
ns
XQV300
-
1.9
ns
XQV600
-
2.3
ns
XQV1000
-
2.7
ns
T_IOPLI
Pad to output IQ via transparent latch, no
delay
All
-
2.0
ns
T_IOPLID
Pad to output IQ via transparent latch, with
XQV100
-
4.8
ns
delay
XQV300
-
5.1
ns
XQV600
-
5.5
ns
XQV1000
-
5.9
ns
Sequential Delays
T_IOCKIQ
Clock CLK to output IQ
Setup and Hold Times with Respect to Clock CLK
All
-
0.8
ns
Setup Time / Hold Time
T_IOPICK / T_IOICKP
T_IOPICKD / T_IOICKPD
T_IOICECK / T_IOCKICE
T_IOSRCKI / T_IOCKISR
Set/Reset Delays
Pad, no delay
Pad, with delay
ICE input
SR input (IFF, synchronous)
All
2.0 / 0 -
ns
All
5.0 / 0 -
ns
All
1.0 / 0 -
ns
All
1.3 / 0 -
ns
T_IOSRIQ
SR input to IQ (asynchronous)
All
-
1.8
ns
T_GSRQ
GSR to output IQ
All
-
12.5
ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”,
but if a “0” is listed, there is no positive hold time.
DS002 (v1.5) December 5, 2001
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