DS573 Datasheet, PDF (9/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Table 2: XPS Timer/Counter Design Parameters (Cont’d)
Generic
Feature / Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
G15
Base address for XPS
Timer/Counter
C_BASEADDR
Valid address
Note⁽¹⁾
std_logic
_vector
G16
High address for XPS
Timer/Counter
C_HIGHADDR
Valid address
Note⁽²⁾
std_logic
_vector
1. Indicates the base address of this peripheral expressed as a std_logic_vector. C_BASEADDR must be a multiple of the
address-range size and the address-range size, C_HIGHADDR - C_BASEADDR + 1, must be a power of two.
2. C_HIGHADDR must be chosen large enough to accommodate the XPS Timer/Counter registers while also guaranteeing a
power-of-two address-range size.
XPS Timer/Counter Parameter Port Dependencies
The dependencies between the XPS Timer/Counter design parameters and the I/O ports are shown in Table 3. The
width of the XPS Timer/Counter signals depend on some of the parameters. In addition, when certain features are
parameterized away, the related logic is remove.
Table 3: Parameter - Port Dependencies
Generic
or Port
Name
Affects
Depends
Description
Design Parameters
G8 C_SPLB_AWIDTH
P3, P11
-
The PLB address width parameter sets the width of the
PLB address bus
G9 C_SPLB_DWIDTH
P7, P10,
P33
The SPLB data width parameter affects the number of
-
byte enables configured for the SPLB data bus, width of
the SPLB data bus and the width of the SPLB slave read
data bus
G11 C_SPLB_MID_WIDTH
P5
G12
C_SPLB_NUM_MASTERS
P36, P37,
P38, P42
G12
The PLB Master ID Bus Width
should be log₂(C_SPLB_NUM_MASTERS)
-
Number of PLB Masters
P3 PLB_ABus
P5 PLB_masterID
P7 PLB_BE
P10 PLB_wrDBus
P11 PLB_UABus
P33 Sl_rdDBus
P36 Sl_MBusy
I/O Signals
-
G8
The PLB address bus width is determined by the
C_SPLB_AWIDTH parameter
-
G11
The PLB master ID is determined by the
C_SPLB_MID_WIDTH parameter
-
G9
The number of byte enables for the PLB data bus is
determined by the C_SPLB_DWIDTH parameter
-
G9
The PLB data bus width is determined by the
C_SPLB_DWIDTH parameter
-
G8
The widht of the PLB upper address bits is determined by
the C_SPLB_AWIDTH parameter
-
G9
The width of the PLB slave read data bus is determined
by the C_SPLB_DWIDTH parameter
-
G12
The width of PLB slave busy is determined by the
C_SPLB_NUM_MASTERS parameter
DS573 April 19, 2010
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Product Specification