DS573 Datasheet, PDF (15/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Table 8: Control/Status Register 1 (TCSR1) (Cont’d)
Bits
Name
Description
Enable External Generate Signal Timer1
29
GENT1
0 = Disables external generate signal
1 = Enables external generate signal
Up/Down Count Timer1
30
UDT1
0 = Timer functions as up counter
1 = Timer functions as down counter
Timer1 Mode
31
MDT1
See the Timer Modes section.
0 = Timer mode is generate
1 = Timer mode is capture
Reset
Value
0
0
0
Implementation
Target Technology
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE Facts table.
Device Utilization and Performance Benchmarks
Core Performance
Because the XPS Timer/Counter core will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates only. System-level results will vary.
The XPS Timer/Counter resource utilization for various parameter combinations measured with the Virtex-4 FPGA
as the target device is detailed in Table 9.
The XPS Timer/Counter resource utilization for various parameter combinations measured with the Virtex-5 FPGA
as the target device is detailed in Table 10.
The XPS Timer/Counter resource utilization for various parameter combinations measured with the Spartan-3
FPGA as the target device is detailed in Table 11.
The XPS Timer/Counter resource utilization for various parameter combinations measured with the Spartan-6
FPGA as the target device is detailed in Table 12.
The XPS Timer/Counter resource utilization for various parameter combinations measured with the Virtex-6 FPGA
as the target device is detailed in Table 13.
DS573 April 19, 2010
www.xilinx.com
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Product Specification