DS573 Datasheet, PDF (3/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
• The counter can be set up to count either up or down as determined by the selection of the UDT bit in the
TCSR. If the counter is set up as a down counter, the generate value is the number of clocks in the timing
interval. The period of the GenerateOut signal is the generate value times the clock period.
• When the counter is set to count down,
• TIMING_INTERVAL = (TLRx + 2) x PLB_CLOCK_PERIOD
• When the counter is set to count up,
• TIMING_INTERVAL = (MAX_COUNT - TLRx + 2) x PLB_CLOCK_PERIOD,
• where MAX_COUNT is the maximum count value of the counter, such as 0xFFFFFFFF for a 32-bit counter.
• The GenerateOut signals can be configured as high-true or low-true.
Capture Mode
In Capture Mode, the value of the counter is stored in the load register when the external capture signal is asserted.
The TINT bit is also set in the Timer Control Status Register (TCSR) on detection of the capture event. The counter
can be configured as an up or down counter for this mode as determined by the selection of the UDT bit in TCSR.
The ARHT bit controls whether the capture value is overwritten with a new capture value before the previous TINT
flag is cleared. This mode is useful for time tagging external events while simultaneously generating an interrupt.
Characteristics
Capture Mode has the following characteristics:
• The capture signal can be configured to be low-true or high-true.
• The capture signal is sampled within the Timer/Counter with the SPLB_Clk. The capture event is defined as
the transition on the sampled signal to the asserted state. For example, if the capture signal is defined to be
high-true, then the capture event is when the sampled signal, synchronized to the SPLB_Clk, transitions from
’0’ to ’1’.
• When the capture event occurs, the counter value is written to the load register. This value is called the capture
value.
• When the ARHT bit (Auto Reload/Hold) is set to ’0’ and the capture event occurs, the capture value is written
to the Load Register which holds the capture value until the load register is read. If the load register is not read,
subsequent capture events will not update the load register, and will be lost.
• When the ARHT bit (Auto Reload/Hold) is set to ’1’, and the capture event occurs, the capture value is always
written to the load register. Subsequent capture events will update the load register and will overwrite the
previous value, whether it has been read or not.
• The counter can be set up to count either up or down as determined by the selection of the UDT bit in the
Timer Control Status Register (TCSR).
Pulse Width Modulation (PWM) Mode
In PWM mode, two timer/counters are used as a pair to produce an output signal (PWM0) with a specified
frequency and duty factor. Timer0 sets the period and Timer1 sets the high time for the PWM0 output.
Characteristics
PWM Mode has the following characteristics:
• The mode for both Timer0 and TImer1 must be set to Generate Mode (bit MDT in the TCSR set to ’0’).
• The PWMA0 bit in TCSR0 and PWMB0 bit in TCSR1 must be set to ’1’ to enable PWM mode.
• The GenerateOut signals must be enabled in the TCSR (bit GENT set to ’1’). The PWM0 signal is generated
from the GenerateOut signals of Timer0 and Timer1, so these signals must be enabled in both timer/counters.
DS573 April 19, 2010
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Product Specification