DS573 Datasheet, PDF (4/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
• The assertion level of the GenerateOut signals for both timers in the pair must be set to ’1’. This is done by
setting C_GEN0_ASSERT and C_GEN1_ASSERT to ’1’.
• The counter can be set to count up or down.
Setting the PWM Period and Duty Factor
The PWM period is determined by the generate value in Timer0’s load register (TLR0). The PWM high time is
determined by the generate value in Timer1’s load register (TLR1). The period and duty factor are calculated as
follows:
When counters are configured to count up (UDT = ’0’):
PWM_PERIOD = (MAX_COUNT - TLR0 + 2) x PLB_CLOCK_PERIOD
PWM_HIGH_TIME = (MAX_COUNT - TLR1 + 2) x PLB_CLOCK_PERIOD
When counters are configured to count down (UDT = ’1’):
PWM_PERIOD = (TLR0 + 2) x PLB_CLOCK_PERIOD
PWM_HIGH_TIME = (TLR1 + 2) x PLB_CLOCK_PERIOD
where MAX_COUNT is the maximum count value for the counter, such as 0xFFFFFFFF for a 32-bit counter.
Interrupts
The TC interrupt signals can be enabled or disabled with the ENIT bit in the TCSR. The interrupt status bit (TINT)
in the TCSR cannot be disabled and always reflects the current state of the timer interrupt. In Generate Mode, a
timer interrupt is caused by the counter rolling over (the same condition used to reload the counter when ARHT is
set to ’1’). In Capture Mode, the interrupt event is the capture event. Characteristics of the interrupts are:
• Interrupt events can only occur when the timer is enabled. In Capture Mode, this prevents interrupts from
occurring before the timer is enabled.
• The interrupt signal goes high when the interrupt condition is met and the interrupt is enabled in the TCSR.
The interrupt is asserted when the interrupt signal is high.
• A single interrupt signal is provided. The interrupt signal is the OR of the interrupts from the two counters.
The interrupt service routine must poll the TCSR’s to determine the source or sources of the interrupt.
• The interrupt status bit (TINT in the TCSR) can only be cleared by writing a ’1’ to it. Writing a ’0’ to it has no
effect on the bit. Since the interrupt condition is an edge (the counter rollover or the capture event), it can be
cleared at any time and will not indicate an interrupt condition until the next interrupt event.
The top level block diagram of the XPS Timer/Counter is shown in Figure 1.
The top level modules of the XPS Timer/Counter are:
• PLB Interface Module
• Timer/Counter
DS573 April 19, 2010
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Product Specification