DS573 Datasheet, PDF (8/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Table 2: XPS Timer/Counter Design Parameters
Generic
Feature / Description
Parameter Name
Allowable Values
System Parameters
G1 Target FPGA family
C_FAMILY
aspartan3, spartan3,
spartan3a, spartan3e,
spartan3adsp, virtex4,
virtex5, virtex5fx,
aspartan3e, aspartan3a,
aspartan3adsp, qvirtex4,
qrvirtex4, spartan6,
virtex6, virtex6cx
XPS Timer/Counter Parameter
The width in bits of the
G2 counters in the XPS
Timer/Counter
C_COUNT_WIDTH
8 - 32
G3 Number of Timer modules
C_ONE_TIMER_ONLY
0 = Two timers are
present
1 = One timer is present
(No PWM mode)
G4
Assertion level for
CaptureTrig0
C_TRIG0_ASSERT
’0’ = CaptureTrig0 input
is low-true
’1’ = CaptureTrig0 input
is high-true
G5
Assertion level for
CaptureTrig1
C_TRIG1_ASSERT
’0’ = CaptureTrig1 input
is low-true
’1’ = CaptureTrig1 input
is high-true
G6
Assertion level for
GenerateOut0
C_GEN0_ASSERT
’0’ = GenerateOut0
output is low-true
’1’ = GenerateOut0
output is high-true
G7
Assertion level for
GenerateOut1
C_GEN1_ASSERT
’0’ = GenerateOut1
output is low-true
’1’ = GenerateOut1
output is high-true
PLB Parameter
G8 PLB address width
C_SPLB_AWIDTH
32
G9 PLB data width
C_SPLB_DWIDTH
32, 64, 128
G10
Selects point-to-point or
shared PLB topology
C_SPLB_P2P
0 = Shared Bus Topology
1 = Point-to-Point Bus
Topology
G11 PLB Master ID Bus Width
C_SPLB_MID_WIDTH
log₂(C_SPLB_NUM_MA
STERS) with a minimum
value of 1
G12 Number of PLB Masters
C_SPLB_NUM_MASTERS 1 - 16
G13 Width of the Slave Data Bus C_SPLB_NATIVE_DWIDTH 32
G14 PLB burst support
C_SPLB_SUPPORT_BURS
TS
0
Default
Value
virtex5
32
0
1
1
1
1
32
32
0
3
8
32
0
VHDL
Type
string
integer
integer
std_logic
std_logic
std_logic
std_logic
integer
integer
integer
integer
integer
integer
integer
DS573 April 19, 2010
www.xilinx.com
8
Product Specification