DS573 Datasheet, PDF (19/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

X-Ref Target - Figure 12
LogiCORE IP XPS Timer/Counter (v1.02a)
MPMC
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
MicroBlaze
Processor
PLBV46
XPS BRAM
XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS573_12_041910
Figure 12: Spartan-6 FPGA System with the XPS Timer/Counter as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 14.
Table 14: XPS XPS Timer/Counter System Performance
Target FPGA
S3A700 -4
Target F_MAX (MHz)
90
V4FX60 -10
100
V5FXT50 -1
120
V6LX130t - 1
150
S6LX45t - 2
100
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Reference Documents
The following documents contain information that may be required in understanding the XPS Timer/Counter
reference design:
1. IBM CoreConnect 128-Bit Processor Local Bus: Architecture Specifications version 4.6
DS573 April 19, 2010
www.xilinx.com
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Product Specification