DS573 Datasheet, PDF (6/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
XPS Timer/Counter I/O Signals
The XPS Timer/Counter I/O signals are listed and described in Table 1.
Table 1: XPS Timer/Counter I/O Signal Description
Port
Signal Name
Interface
I/O
Initial
Status
Description
System Signals
P1 SPLB_Clk
P2 SPLB_Rst
PLB
I
-
PLB clock
PLB
I
-
PLB reset, active high
PLB Slave Interface Input Signals
P3 PLB_ABus[0 to C_SPLB_AWIDTH - 1]
PLB
I
-
PLB address bus
P4 PLB_PAValid
PLB
I
-
PLB primary address valid
P5 PLB_masterID[0 : C_SPLB_MID_WIDTH - 1]
PLB
I
-
PLB current master identifier
P6 PLB_RNW
PLB
I
-
PLB read not write
P7 PLB_BE[0 : (C_SPLB_DWIDTH/8) - 1]
PLB
I
-
PLB byte enables
P8 PLB_size[0 : 3]
PLB
I
-
PLB byte enables
P9 PLB_type[0 : 2]
PLB
I
-
PLB transfer type
P10 PLB_wrDBus[0 : C_SPLB_DWIDTH - 1]
PLB
I
-
PLB write data bus
Unused PLB Slave Interface Input Signals
P11 PLB_UABus[0 to C_SPLB_AWIDTH - 1]
P12 PLB_SAValid
P13 PLB_rdPrim
P14 PLB_wrPrim
P15 PLB_abort
P16 PLB_busLock
P17 PLB_MSize
P18 PLB_lockErr
P19 PLB_wrBurst
P20 PLB_rdBurst
P21 PLB_wrPendReq
P22 PLB_rdPendReq
P23 PLB_wrPendPri[0 : 1]
P24 PLB_rdPendPri[0 : 1]
P25 PLB_reqPri[0 : 1]
P26 PLB_TAttribute
PLB
I
-
PLB upper address bits
PLB
I
-
PLB secondary address valid
PLB
I
-
PLB secondary to primary read
request indicator
PLB
I
-
PLB secondary to primary write
request indicator
PLB
I
-
PLB abort bus request
PLB
I
-
PLB bus lock
PLB
I
-
PLB data bus port width
indicator
PLB
I
-
PLB lock error
PLB
I
-
PLB burst write transfer
PLB
I
-
PLB burst read transfer
PLB
I
-
PLB pending bus write request
PLB
I
-
PLB pending bus read request
PLB
I
-
PLB pending write request
priority
PLB
I
-
PLB pending read request
priority
PLB
I
-
PLB current request priority
PLB
I
-
PLB transfer attribute
PLB Slave Interface Output Signals
DS573 April 19, 2010
www.xilinx.com
6
Product Specification