DS573 Datasheet, PDF (17/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Table 13: Performance and Resource Utilization Benchmarks for the Virtex-6 FPGA (xc6vlx195t-ff11562-1)
Parameter Values
Device Resources
Performance
C_ONE_TIMER_ONLY
0
C_COUNT_WIDTH
32
Slice Flip-Flops
186
LUTs
365
f_{MAX (MHz)}
203
0
16
121
232
202
0
8
89
174
203
1
32
117
217
202
1
16
84
149
201
1
8
68
124
209
System Performance
To measure the system performance (F_MAX) of this core, this core was added to a Virtex-4 FPGA system, a Virtex-5
system FPGA, Spartan-3A FPGA system, Virtex-6 FPGA system and a Spartan-6 FPGA system as the Device Under
Test (DUT) as shown in Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12.
Because the XPS Timer/Counter core will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates only. When this core is combined with other designs in the
system, the utilization of FPGA resources and timing of the core design will vary from the results reported here.
X-Ref Target - Figure 8
PLBV46
PLBV46
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
DPLB0
PowerPC 405
Processor ^IPLB0
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
DS582_08_041910
Figure 8: Virtex-4 FX FPGA System with the XPS Timer/Counter as the DUT
DS573 April 19, 2010
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Product Specification