DS573 Datasheet, PDF (13/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Table 7: Control/Status Register 0 (TCSR0) (Cont’d)
Bits
Name
Description
Load Timer0
26
LOAD0
0 = No load
1 = Loads timer with value in TLR0
Auto Reload/Hold Timer0
When the timer is in Generate Mode, this bit determines whether the counter
reloads the generate value and continues running or holds at the termination
27
ARHT0
value. In Capture Mode, this bit determines whether a new capture trigger
overwrites the previous captured value or if the previous value is held.
0 = Hold counter or capture value
1 = Reload generate value or overwrite capture value
Enable External Capture Trigger Timer0
28
CAPT0
0 = Disables external capture trigger
1 = Enables external capture trigger
Enable External Generate Signal Timer0
29
GENT0
0 = Disables external generate signal
1 = Enables external generate signal
Up/Down Count Timer0
30
UDT0
0 = Timer functions as up counter
1 = Timer functions as down counter
Timer0 Mode
31
MDT0
See the Timer Modes section.
0 = Timer mode is generate
1 = Timer mode is capture
Reset
Value
0
0
0
0
0
0
Control/Status Register 1 (TCSR1)
The Figure 7 and Table 8 shows the Control/Status register 1. Control/Status Register 1 contains the control and
status bits for timer module 1.
X-Ref Target - Figure 7
ENALL
T1INT
ENIT1
ARHT1
GENT1
MDT1
0
20 21 22 23 24 25 26 27 28 29 30 31
Reserved
PWMA0
LOAD1
UDT1
ENT1
CAPT1
DS573_07_041910
Figure 7: Timer/Status Control Register 1 (TSCR1)
DS573 April 19, 2010
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Product Specification