DS573 Datasheet, PDF(14/20 Page) Xilinx, Inc – PLB interface with byte-enable support

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DS573 Datasheet, PDF (14/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

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LogiCORE IP XPS Timer/Counter (v1.02a)

Table 8: Control/Status Register 1 (TCSR1)

Bits

Name

Description

0 - 20

Reserved

ENALL

PWMB0

T1INT

ENT1

ENIT1

LOAD1

ARHT1

CAPT1

Reserved

Enable All Timers

0 = No effect on timers

1 = Enable all timers (counters run)

This bit is mirrored in all control/status registers and is used to enable all

counters simultaneously. Writing a â1â to this bit sets ENALL, ENT0, and

ENT1. Writing a â0â to this register clears ENALL but has no effect on ENT0

and ENT1.

Enable Pulse Width Modulation for Timer1

0 = Disable pulse width modulation

1 = Enable pulse width modulation

PWM requires using Timer0 and Timer1 together as a pair. Timer0 sets the

period of the PWM output, and Timer1 sets the high time for the PWM output.

For PWM Mode, MDT0 and MDT1 must be â0â and C_GEN0_ASSERT and

C_GEN1_ASSERT must be â1â.

Timer1 Interrupt

Indicates that the condition for an interrupt on this timer has occurred. If the

timer mode is capture and the timer is enabled, this bit indicates a capture

has occurred. If the mode is generate, this bit indicates the counter has rolled

over. Must be cleared by writing a â1â.

Read:

0 = No interrupt has occurred

1 = Interrupt has occurred

Write:

0 = No change in state of T1INT

1 = Clear T1INT (clear to â0â)

Enable Timer1

0 = Disable timer (counter halts)

1 = Enable timer (counter runs)

Enable Interrupt for Timer1

Enables the assertion of the interrupt signal for this timer. Has no effect on

the interrupt flag in TCSR1.

0 = Disable interrupt signal

1 = Enable interrupt signal

Load Timer1

0 = No load

1 = Loads timer with value in TLR1

Auto Reload/Hold Timer1

When the timer is in generate mode, this bit determines whether the counter

reloads the generate value and continues running or holds at the termination

value. In capture mode, this bit determines whether a new capture trigger

overwrites the previous captured value or if the previous value is held until it

is read.

0 = Hold counter or capture value

1 = Reload generate value or overwrite capture value

Enable External Capture Trigger Timer1

0 = Disables external capture trigger

1 = Enables external capture trigger

Reset

Value

DS573 April 19, 2010

www.xilinx.com

Product Specification

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