DS573 Datasheet, PDF (2/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Functional Description
The Timer/Counter is organized as two identical timer modules as shown in Figure 2. Each timer module has an
associated load register that is used to hold either the initial value for the counter for event generation, or a capture
value, depending on the mode of the timer.
The generate value is used to generate a single interrupt at the expiration of an interval, or a continuous series of
interrupts with a programmable interval. The capture value is the timer value that has been latched on detection of
an external event. The clock rate of the timer modules is SPLB_Clk (no prescaling of the clock is performed). All of
the Timer/Counter interrupts are OR’ed together to generate a single external interrupt signal. The interrupt
service routine reads the control/status registers to determine the source of the interrupt.
Programming Model
Timer Modes
There are three modes that can be used with the two Timer/Counter modules:
• Generate mode
• Capture mode
• Pulse Width Modulation (PWM) mode.
The modes and their characteristics are described in the following sections.
Generate Mode
In the Generate mode, the value in the load register is loaded into the counter. The counter, when enabled, begins
to count up or down, depending on the selection of the UDT bit in the Timer Control Status Register (TCSR). See
Figure 6 and Figure 7. On transition of the carry out of the counter, the counter stops or automatically reloads the
generate value from the load register and continues counting as selected by the ARHT bit in the TCSR. The TINT bit
is set in TCSR and, if enabled, the external GenerateOut signal is driven to 1 for one clock cycle. If enabled, the
interrupt signal for the timer is driven to 1 for one clock cycle. This mode is useful for generating repetitive
interrupts or external signals with a specified interval.
Characteristics
The generate mode has the following characteristics:
• The value loaded into the load register is called the generate value.
• On startup, the generate value in the load register must be loaded into the counter by setting the Load bit in
the Timer Control Status Register (TCSR). This applies whether the counter is set up to Auto Reload or Hold
when the interval has expired. Setting the Load bit to ’1’ loads the counter with the value in the load register.
For proper operation, the Load bit must be cleared before the counter is enabled.
• When the ARHT bit (Auto Reload/Hold) is set to ’1’ and the counter rolls over from all ’1’s to all ’0’s when
counting up, or conversely from all ’0’s to all ’1’s when counting down, the generate value in the load register
will be automatically reloaded into the counter and the counter will continue to count. If the GenerateOut
signal is enabled (bit GENT in the TCSR), an output pulse will be generated (one clock period in width). This is
useful for generating a repetitive pulse train with a specified period.
• When the ARHT bit (Auto Reload/Hold) is set to ’0’ and the counter rolls over from all ’1’s to all ’0’s, when
counting up, or conversely, from all ’0’s to all ’1’s, when counting down, the counter will hold at the current
value and will not reload the generate value. If the generate out signal is enabled (bit GENT in the TCSR), an
output pulse of one clock period in width will be generated. This is useful for a one-shot pulse that is to be
generated after a specified period of time.
DS573 April 19, 2010
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Product Specification