DS573 Datasheet, PDF (10/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Table 3: Parameter - Port Dependencies (Cont’d)
Generic
or Port
Name
Affects Depends
Description
P37 Sl_MWrErr
-
G12
The width of PLB slave write error is determined by the
C_SPLB_NUM_MASTERS parameter
P38 Sl_MRdErr
-
G12
The width of PLB slave read error is determined by the
C_SPLB_NUM_MASTERS parameter
P42 Sl_MIRQ
-
G12
The width of Master interrupt request is determined by
the C_SPLB_NUM_MASTERS parameter
Register Data Types and Organization
Timer Counter registers are accessed as one of the following types:
• Byte (8 bits)
• Half word (2 bytes)
• Word (4 bytes)
The XPS Timer/Counter registers are organized as big-endian data. The bit and byte labeling for the big-endian
data types is shown in the Figure 3.
X-Ref Target - Figure 3
Byte address
n
n+1
n+2
n+3
Byte label
0
1
2
3
Word
Byte significance MS Byte
LS Byte
Bit label 0
31
Bit significance _{MS Bit}
LS Byte
Byte address
n
Byte label
0
Byte significance MS Byte
Bit label 0
Bit significance MS Bit
n+1
1
Halfword
LS Byte
15
LS Bit
Byte address
n
Byte label
0
Byte
Byte significance MS Byte
Bit label 0
7
Bit significance MS Bit LS Bit
Figure 3: Big-Endian Data Types
DS573_03_041910
DS573 April 19, 2010
www.xilinx.com
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