DS573 Datasheet, PDF (7/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Table 1: XPS Timer/Counter I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
Status
Description
P27 Sl_addrAck
PLB
O
0 Slave address acknowledge
P28 Sl_SSize[0 : 1]
PLB
O
0 Slave data bus port size
P29 Sl_wait
PLB
O
0 Slave wait
P30 Sl_rearbitrate
PLB
O
0 Slave bus rearbitrate
P31 Sl_wrDAck
PLB
O
0 Slave write data acknowledge
P32 Sl_wrComp
PLB
O
0 Slave write transfer complete
P33 Sl_rdDBus[0 : C_SPLB_DWIDTH - 1]
PLB
O
0 Slave read data bus
P34 Sl_rdDAck
PLB
O
0 Slave read data acknowledge
P35 Sl_rdComp
PLB
O
0 Slave read transfer complete
P36 Sl_MBusy[0 C_SPLB_NUM_MASTERS - 1]
PLB
O
0 Slave busy
P37 Sl_MWrErr[0 : C_SPLB_NUM_MASTERS - 1] PLB
O
0 Slave write error
P38 Sl_MRdErr[0 : C_SPLB_NUM_MASTERS - 1] PLB
O
0 Slave read error
Unused PLB Slave interface Output Signals
P39 Sl_wrBTerm
PLB
O
0
Slave terminate write burst
transfer
P40 Sl_rdWdAddr[0 : 3]
PLB
O
0 Slave read word address
P41 Sl_rdBTerm
PLB
O
0
Slave terminate read burst
transfer
P42 Sl_MIRQ[0 : C_SPLB_NUM_MASTERS - 1]
PLB
O
0 Master interrupt request
XPS Timer/Counter Signals
P43 CaptureTrig0
Ext.
I
-
Capture Trigger 0
P44 CaptureTrig1
Ext.
I
-
Capture Trigger 1
P45 Freeze
Ext.
I
-
Freeze Count Value
P46 GenerateOut0
Ext.
O
0 Generate Output 0
P47 GenerateOut1
Ext.
O
0 Generate Output 1
P48 PWM0
Ext.
O
0
Pulse Width Modulation Output
0
P49 Interrupt
Ext.
O
0 Interrupt
XPS Timer/Counter Design Parameters
To allow the user to create the XPS Timer/Counter that is uniquely tailored for the user’s system, certain features
can be parameterized in the XPS Timer/Counter design. This allows the user to have a design that only utilizes the
resources required by the system and operating at the best possible performance. The features that are
parameterizable in the XPS Timer/Counter are as shown in Table 2.
DS573 April 19, 2010
www.xilinx.com
7
Product Specification