DS573 Datasheet, PDF (11/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
Register Descriptions
The addresses of the XPS Timer/ Counter registers are shown in the Table 4.
Table 4: XPS Timer/Counter Register Address Map
Register
Address (Hex)
Size
TCSR0
C_BASEADDR + 0x00
Word
TLR0
C_BASEADDR + 0x04
Word
TCR0
C_BASEADDR + 0x08
Word
TCSR1
C_BASEADDR + 0x10
Word
TLR1
C_BASEADDR + 0x14
Word
TCR1
C_BASEADDR + 0x18
Word
Type
Read/Write
Read/Write
Read
Read/Write
Read/Write
Read
Description
Control/Status Register 0
Load Register 0
Timer/Counter Register 0
Control/Status Register 1
Load Register 1
Timer/Counter Register 1
Load Register (TLR0 and TLR1)
When the counter width has been configured as less than 32 bits, the load register value is right-justified in TLR0
and TLR1. The least-significant counter bit is always mapped to load register bit 31. The Figure 4 and Table 5 shows
the load register.
X-Ref Target - Figure 4
0
31
TLRx
Figure 4: Timer/Counter Load Register (TLR)
Table 5: Timer/Counter Load Register
Bits
Name
0 - 31 Timer/Counter Load Register
Description
Timer/Counter Load register
DS573_04_041910
Reset Value
0
Timer/Counter Register (TCR0 and TCR1)
When the counter width has been configured as less than 32 bits, the count value is right-justified in TCR0 and
TCR1. The least-significant counter bit is always mapped to Timer/Counter Register bit 31. The Figure 5 and
Table 6 shows the Timer/counter register.
X-Ref Target - Figure 5
0
31
TCRx
Figure 5: Timer/Counter Register (TCR)
Table 6: Timer/Counter Register
Bits
Name
0 - 31 Timer/Counter Register
Description
Timer/Counter register
DS573_04_041910
Reset Value
0
DS573 April 19, 2010
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Product Specification