DS573 Datasheet, PDF (5/20 Pages) Xilinx, Inc – PLB interface with byte-enable support

LogiCORE IP XPS Timer/Counter (v1.02a)
X-Ref Target - Figure 1
PLB BUS
XPS TIMER/COUNTER
PLB Interface
Module
bus2ip_clk
bus2ip_reset
bus2ip_addr
bus2ip_be
bus2ip_data
ip2bus_data
bus2ip_rdce
bus2ip_wrce
ip2bus_rdack
ip2bus_wrack
ip2bus_error
Timer/Counter
CaptureTrig0
CaptureTrig1
GenerateOut0
GenerateOut1
PWM0
Interrupt
Freeze
DS573_01_041910
Figure 1: XPS Timer/Counter Top-Level Block Diagram
The detailed block diagram of the XPS Timer/Counter is shown in Figure 2.
X-Ref Target - Figure 2
PLB Interface Module
CaptureTrig0
CaptureTrig1
TCSR0 ^{Control/Status}
TCSR1 ^{Control/Status}
Load Register
TRL0
TRL0
32b Counter
Load Register
TRL1
TRL1
32b Counter
Interrupt Logic
TC_Interrupt
GenerateOut0
PWM0
GenerateOut1
DS573_02_041910
Figure 2: XPS Timer/Counter Detailed Block Diagram
DS573 April 19, 2010
www.xilinx.com
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Product Specification