DS810 Datasheet, PDF (6/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 1: I/O Signal Description (Cont’d)
Signal Name
Interface Signal Type
MON_AXI_S_TUSER(C_MON_
AXI_S_TUSER_WIDTH-1:0)
AXI4-Stream
I
Init
Status
Description
AXI-Stream user data
Notes:
1. If the ChipScope AXI Monitor is connected to a core that does not have the AXI4 ARESETN signal, the signal is shown as a
constant 0 in the Chipscope Analyzer, but otherwise does not assert reset or affect the behavior of the ChipScope AXI Monitor. If
an auxiliary reset signal is needed, manually connect this signal to the Trigger In port of the ChipScope AXI Monitor.
Design Parameters
The core design parameters are listed and described in Table 2.
Table 2: Design Parameters
Feature Description
Parameter Name
Allowable Values
User Specified AXI Implemented Parameters
Active bus interface type
C_USE_INTERFACE
(0: AXI4/AXI4-Lite,
1: AXI4-Stream,
2: AXI3 Memory map)
Sets number of data samples C_NUM_DATA_SAMPLES
(1024, 2048, 4096, 8192,
16384, 32768, 65536,
131072)
Maximum number of
sequencer levels
C_MAX_SEQUENCER_LEVELS
2
Enable trigger in
C_USE_TRIG_IN
(0,1)
Trigger input width
C_TRIG_IN_WIDTH
(1:255)
AWLEN/ARLEN Bus Width
C_MON_AXI_BURST_LENGTH
(4,8)
AWLOCK/ARLOCK Bus Width C_MON_AXI_LOCK_LENGTH
(1,2)
ARADDR Number of Match
Units
C_MON_AXI_ARADDR_NUM_OF_
MATCH
(0:4)
ARADDRCONTROL Number C_MON_AXI_ARADDRCONTROL
of Match Units
_NUM_OF_MATCH
(0:4)
AWADDR Number of Match
Units
C_MON_AXI_AWADDR_NUM_OF
_MATCH
(0:4)
AWADDRCONTROL Number C_MON_AXI_AWADDRCONTROL
of Match Units
_NUM_OF_MATCH
(0:4)
BRESP Number of Match Units
C_MON_AXI_BRESP_NUM_OF_M
ATCH
(0:4)
GLOBAL Number of Match
Units
C_MON_AXI_GLOBAL_NUM_OF_
MATCH
(0:4)
RDATA Number of Match Units
C_MON_AXI_RDATA_NUM_OF_M
ATCH
(0:4)
RDATACONTROL Number of C_MON_AXI_RDATACONTROL_N
Match Units
UM_OF_MATCH
(0:4)
C_MON_AXI_WDATA_NUM_
WDATA Number of Match Units _{OF_MATCH}
(0:4)
Default
Values
Type
0
integer
1048
(1:16)
0
1
8
1
1
1
1
1
1
1
1
1
1
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
DS810 July 25, 2012
www.xilinx.com
6
Product Specification