DS810 Datasheet, PDF (12/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 2: Design Parameters (Cont’d)
Feature Description
Parameter Name
Allowable Values
Write address USER port bus
width
C_MON_AXI_AWUSER_WIDTH
(1:256)⁽¹⁾
Write data USER port bus
width
C_MON_AXI_WUSER_WIDTH
(1:256)⁽¹⁾
Write response USER port
bus width
C_MON_AXI_BUSER_WIDTH
(1:256)⁽¹⁾
Read address USER port bus
width
C_MON_AXI_ARUSER_WIDTH
(1:256)⁽¹⁾
Read data USER port bus
width
C_MON_AXI_RUSER_WIDTH
(1:256)⁽¹⁾
Streaming USER port bus
width
C_MON_AXI_S_TUSER_WIDTH
(1:256)⁽¹⁾
System supports read
operations
C_MON_AXI_SUPPORTS_READ
(0,1)
System supports write
operations
C_MON_AXI_SUPPORTS_WRITE
(0,1)
AXI Protocol Checker Parameters
Protocol Checker Number of C_MON_AXI_PC_NUM_OF_
Match Units
MATCH
(0:1)
Protocol Checker Match Type C_MON_AXI_PC_MATCH_TYPE
(basic=basic, basic with
edges=basic with edges,
extended=extended,
extended with
edges=extended with
edges, range=range, range
with edges=range with
edges)
Protocol Checker Trigger
Counter Width
C_MON_AXI_PC_TRIG_COUNT_
WIDTH
(1:32)
Protocol Checker Trigger
Store/Trace to ILA Data Port
C_MON_AXI_PC_TRACE
(0: Do Not Store, 1: Store)
Handshake Protocol Checks
Enable (Trigger
PC_ERROR_HANDSHAKE_
OR)
C_MON_AXI_EN_HANDSHAKE_
CHECKS
(0,1)
Complex Protocol Checks
Enable (Trigger
PC_ERROR_COMPLEX_OR)
C_MON_AXI_EN_COMPLEX_
CHECKS
(0,1)
Exclusive Access Protocol
Checks Enable (Trigger
PC_ERROR_EXCLUSIVE_O
R)
C_MON_AXI_EN_EXCLUSIVE_
CHECKS
(0,1)
Illegal Value Protocol Checks
Enable (Trigger
PC_ERROR_ILLEGAL_VALU
E_OR)
C_MON_AXI_EN_ILLEGAL_
VALUE_CHECKS
(0,1)
Reset Protocol Checks Enable
(Trigger
PC_ERROR_RESET_OR)
C_MON_AXI_EN_RESET_CHECK
S
(0,1)
Default
Values
1
1
1
1
1
1
1
1
0
basic with
edges
1
0
0
0
0
0
0
Type
integer
integer
integer
integer
integer
integer
integer
integer
integer
string
integer
string
integer
integer
integer
integer
integer
DS810 July 25, 2012
www.xilinx.com
12
Product Specification