DS810 Datasheet, PDF (15/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 3: AXI Protocol Checks and Descriptions (Cont’d)
Name of Protocol Check
Enabling Parameter
AXI4_ERRS_RRESP_
STABLE
C_AXI_PC_EN_HANDSHAKE_CHECKS
AXI4_ERRS_RVALID_
STABLE
C_AXI_PC_EN_HANDSHAKE_CHECKS
AXI4_ERRM_AWUSER_STABLE
C_AXI_PC_EN_HANDSHAKE_CHECKS
AXI4_ERRM_WUSER_
STABLE
C_AXI_PC_EN_HANDSHAKE_CHECKS
AXI4_ERRS_BUSER_
STABLE
C_AXI_PC_EN_HANDSHAKE_CHECKS
AXI4_ERRM_ARUSER_
STABLE
C_AXI_PC_EN_HANDSHAKE_CHECKS
AXI4_ERRS_RUSER_
STABLE
C_AXI_PC_EN_HANDSHAKE_CHECKS
AXI4_ERRM_AWADDR_BOUNDARY C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4_ERRM_AWADDR_WRAP_ALIG
N
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4_ERRM_AWBURST
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4_ERRM_AWCACHE
AXI4_ERRM_AWLEN_
FIXED
AXI4_ERRM_AWLEN_
WRAP
AXI4_ERRM_AWSIZE
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4_ERRM_WSTRB
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4_ERRM_ARADDR_
BOUNDARY
AXI4_ERRM_ARADDR_WRAP_ALIG
N
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4_ERRM_ARBURST
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4_ERRM_ARCACHE
AXI4_ERRM_ARLEN_
FIXED
AXI4_ERRM_ARLEN_
WRAP
AXI4_ERRM_ARSIZE
AXI4_ERRM_AWLEN_LOCK
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_EXCLUSIVE_CHECKS
Description
RRESP must remain stable when RVALID is
asserted and RREADY low
Once RVALID is asserted, it must remain
asserted until RREADY is high
AWUSER must remain stable when
AWVALID is asserted and AWREADY low
WUSER must remain stable when WVALID
is asserted and WREADY low
BUSER must remain stable when BVALID is
asserted and BREADY low
ARUSER must remain stable when
ARVALID is asserted and ARREADY low
RUSER must remain stable when RVALID is
asserted and RREADY low
A write burst cannot cross a 4KB boundary
A write transaction with burst type WRAP
has an aligned address
A value of 2’b11 on AWBURST is not
permitted when AWVALID is HIGH
If not cacheable (AWCACHE[1] == 1'b0),
AWCACHE = 2'b00
Transactions of burst type FIXED cannot
have a length greater than 16 beats
A write transaction with burst type WRAP
has a length of 2, 4, 8, or 16
The size of a write transfer does not exceed
the width of the data interface
Write strobes must only be asserted for the
correct byte lanes as determined from the:
Start Address, Transfer Size and Beat
Number
A read burst cannot cross a 4KB boundary
A read transaction with a burst type of
WRAP must have an aligned address
A value of 2'b11 on ARBURST is not
permitted when ARVALID is HIGH
When ARVALID is HIGH, if ARCACHE[1] is
LOW, then ARCACHE[3:2] must also be
LOW
Transactions of burst type FIXED cannot
have a length greater than 16 beats
A read transaction with burst type of WRAP
must have a length of 2, 4, 8, or 16
The size of a read transfer must not exceed
the width of the data interface
Exclusive access transactions cannot have
a length greater than 16 beats
DS810 July 25, 2012
www.xilinx.com
15
Product Specification