DS810 Datasheet, PDF (3/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
AXI Protocol Checker
The AXI Protocol Checker can be optionally included in the ChipScope AXI Monitor to check for AXI4-Memory
Map and AXI4-Lite Protocol violations. The AXI Protocol Checker is designed around the ARM system verilog
assertions which have been converted into synthesizable HDL. The AXI Protocol Checker supplies a flag to the ILA
which can be triggered on when a violation of the protocol is detected.
Upon enabling the AXI Protocol Checker, the user will be given a choice as to which types of protocol checks are to
be monitored (See Note 1). See Table 3 for the complete list of protocol checks or see the AMBA® AXI4, AXI4-Lite,
and AXI4-Stream Protocol Assertions User Guide. When the user enables a group of protocol checks, that group of
flags will be OR’ed, then the OR’ed signal will be connected to a trigger port of the ChipScope ILA core. If the
C_MON_AXI_PC_TRACE parameter is set to Store, the actual error flags will be connected to the DATA port of the
ILA and will be able to be monitored. It is important to note that the user must trace the AXI signals that correspond
to the protocol check to determine where a protocol violation occurs. Depending on the protocol check, the latency
of the violation flag triggering data capture, can occur from one to three clock cycles after the violation has occurred.
It is necessary to position the violation flag trigger inside the capture window to more than 3 samples in the position
entry to ensure that the AXI protocol violation will be displayed.
1. For the ChipScope AXI Monitor core, you can enable the Chks only.
I/O Signals
The core I/O signals are listed and described in Table 1.
Table 1: I/O Signal Description
Signal Name
Interface
Signal Type
Init
Status
Description
CHIPSCOPE_ICON_
CONTROL(35:0)
MON_AXI_TRIG_OUT
AXI4 Memory Map Signals
N/A
I/O
Control bus connection to the ICON core.
Mandatory.
Note: For XPS designs, the direction of this port
is IN.
N/A
O
Trigger output port. (Optional)
MON_AXI_TRIG_IN
N/A
I
Trigger input port. (Optional)
MON_AXI_ACLK
AXI4
I
Clock
MON_AXI_ARESETN ⁽¹⁾
AXI4
I
Reset (active low)
MON_AXI_AWID(C_MON_AXI_
ID_WIDTH-1:0)
AXI4
I
Write address channel transaction ID
MON_AXI_AWADDR(C_MON_
AXI_ADDR_WIDTH-1:0)
AXI4
I
Write address channel address
MON_AXI_AWLEN(7:0)
AXI4
I
Write address burst length: Gives the exact
number of transfers in a burst
MON_AXI_AWSIZE(2:0)
AXI4
I
Write address burst size: Indicates the size of
each transfer in the burst
MON_AXI_AWBURST(1:0)
AXI4
I
Write address burst type
MON_AXI_AWLOCK
AXI4
I
Write address lock type
MON_AXI_AWCACHE(3:0)
AXI4
I
Write address cache type
MON_AXI_AWPROT(2:0)
AXI4
I
Write address protection type
DS810 July 25, 2012
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Product Specification