DS810 Datasheet, PDF(4/21 Page) Xilinx, Inc – LogiCORE IP ChipScope AXI

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DS810 Datasheet, PDF (4/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

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LogiCORE IP ChipScope AXI Monitor (v3.05.a)

Table 1: I/O Signal Description (Contâd)

Signal Name

Interface

MON_AXI_AWQOS(3:0)

MON_AXI_AWREGION(3:0)

AXI4

AXI4

MON_AXI_AWVALID

AXI4

MON_AXI_AWREADY

MON_AXI_AWUSER

MON_AXI_WID(C_MON_AXI_

ID_WIDTH)-1:0)

MON_AXI_WDATA(C_MON_

AXI_DATA_WIDTH-1:0)

MON_AXI_WSTRB(C_MON_

AXI_DATA_WIDTH/8)-1:0)

MON_AXI_WLAST

AXI4

AXI4

AXI3

AXI4

AXI4

AXI4

MON_AXI_WVALID

AXI4

MON_AXI_WREADY

MON_AXI_WUSER

MON_AXI_BID(C_MON_AXI_

ID_WIDTH-1:0)

MON_AXI_BRESP(1:0)

AXI4

AXI4

AXI4

AXI4

MON_AXI_BVALID

AXI4

MON_AXI_BREADY

AXI4

MON_AXI_BUSER

MON_AXI_ARID(C_MON_AXI_

ID_WIDTH-1:0)

MON_AXI_ARADDR(C_MON_

AXI_ADDR_WIDTH-1:0)

MON_AXI_ARLEN(7:0)

MON_AXI_ARSIZE(2:0)

AXI4

AXI4

AXI4

AXI4

AXI4

Signal Type

I

I

I

I

I

Init

Status

Description

Write address channel quality of service

Selects address range within multirange slave

Write address valid: Indicates a valid write

address and control information is available

Write address ready: slave is ready to accept

address and control information

Write address channel USER signals

I

Write data channel transaction ID

I

Write data bus

Write strobes: Indicates which byte lanes have

I

valid data. MON_AXI_WSTRB[n] corresponds to

MON_AXI_WDATA[(8xn)]+7:(8xn)]

I

Indicates last write data word

Write valid: Indicated valid write data and strobes

are available.

I

1 = write data and strobes available

0 = write data and strobes not available

Write ready: Indicates the slave can accept the

write data

I

1= slave ready

0 = slave not ready

I

Write data channel USER signals

I

Write response channel ID

I

Write response: Indicates the status of the write

transaction

Write response valid: Indicates a valid write

response is available

I

1= write response available

0 = write response not available

Write response ready: Indicates the master can

accept the response information

I

1 = master ready

0 = master not ready

I

Write response channel USER signals

I

Read address ID

I

Read address bus

I

Read address burst length: Gives the exact

number of transfers in a burst

I

Read address burst size: Indicates the size of

each transfer in the burst

DS810 July 25, 2012

www.xilinx.com

4

Product Specification

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