DS810 Datasheet, PDF (2/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Functional Description
The AXI Monitor is used to debug top-level signals in a system that uses AXI4 protocol specifications by connecting
it to an AXI Core using Xilinx® Platform Studio (XPS). When placed in an AXI system, the connection of the AXI
Monitor probes between the AXI Interconnect and the AXI Core. The signal list is shown in Table 1. The user can
monitor either AXI Memory Map signals through the MON_AXI bus interface or AXI Streaming signals through
the MON_AXI_S bus interface (but not both) with a single AXI Monitor core. Communication with the ILA core is
conducted using a connection to the JTAG port through the ICON core. See Figure 1.
X-Ref Target - Figure 1
Chipscope AXI Monitor
Chipscope Pro
ICON Core
Control 0
Chipscope Pro
ILA Core
Control
AXI4 Protocol
Checker Core
AXI4 Memory Map
and
AXI4-Lite Interface
AXI3
Interface
MON_AXIBus
MON_AXI
(Subset) Bus
AXI4-Stream
Interface
MON_AXI_SBus
TRIG_IN
TRIG_OUT
Figure 1: ChipScope AXI Monitor Block Diagram
DS810_01
The AXI Monitor is a wrapper for the ChipScope ILA core. It functions the same way as the ChipScope ILA, except
that the wrapper creates a specific ILA for monitoring AXI signals by creating trigger groups designed for
debugging purposes. When connected to a core in an AXI system, the user will specify which bus interface is to be
connected (AXI4 Memory Map, AXI4-Streaming, AXI3), then supply values for parameters such as sample size and
enable trigger out. These parameters are listed in Table 2.
After downloading the bitstream from the design to the FPGA, the ChipScope Analyzer Software tool is used to set
up triggering and view waveforms from the system. The core generates a CDC file which is used by the ChipScope
Analyzer tool to label the AXI signals with the appropriate header information and to define the trigger groups.
More information on the ChipScope ILA or the ChipScope Analyzer can be found in the DS299 ChipScope ILA
document and the UG029 ChipScope Analyzer document.
The AXI Monitor core is capable of using multiple AXI Monitors in a single AXI system to monitor multiple cores
or can be used together by creating a trigger condition for the TRIG_OUT port from one monitor, then connecting
it to the TRIG_IN port of another monitor. In XPS, when instantiating the AXI Monitor, connect the trigger out and
trigger in pins on separate monitors, then use the ChipScope Analyzer to create the trigger condition on the specific
monitor which will trigger the other to begin capturing data.
DS810 July 25, 2012
www.xilinx.com
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Product Specification