DS810 Datasheet, PDF (11/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 2: Design Parameters (Cont’d)
Feature Description
Parameter Name
Allowable Values
BRESP Trigger Store/Trace to
ILA Data Port
C_MON_AXI_BRESP_TRACE
(0: Do Not Store, 1: Store)
ARADDRCONTROL Trigger
Store/Trace to ILA Data Port
C_MON_AXI_ARADDRCONTROL
_TRACE
(0: Do Not Store, 1: Store)
ARADDR Trigger Store/Trace
to ILA Data Port
C_MON_AXI_ARADDR_TRACE
(0: Do Not Store, 1: Store)
RDATACONTROL Trigger
Store/Trace to ILA Data Port
C_MON_AXI_RDATACONTROL_
TRACE
(0: Do Not Store, 1: Store)
RDATA Trigger Store/Trace to
ILA Data Port
C_MON_AXI_RDATA_TRACE
(0: Do Not Store, 1: Store)
AWUSER Trigger Store/Trace
to ILA Data Port
C_MON_AXI_AWUSER_TRACE
(0: Do Not Store, 1: Store)
WUSER Trigger Store/Trace to
ILA Data Port
C_MON_AXI_WUSER_TRACE
(0: Do Not Store, 1: Store)
BUSER Trigger Store/Trace to
ILA Data Port
C_MON_AXI_BUSER_TRACE
(0: Do Not Store, 1: Store)
ARUSER Trigger Store/Trace
to ILA Data Port
C_MON_AXI_ARUSER_TRACE
(0: Do Not Store, 1: Store)
RUSER Trigger Store/Trace to
ILA Data Port
C_MON_AXI_RUSER_TRACE
(0: Do Not Store, 1: Store)
TCONTROL Trigger
Store/Trace to ILA Data Port
C_MON_AXI_S_TCONTROL_
TRACE
(0: Do Not Store, 1: Store)
TDATA Trigger Store/Trace to
ILA Data Port
C_MON_AXI_S_TDATA_TRACE
(0: Do Not Store, 1: Store)
TUSER Trigger Store/Trace to
ILA Data Port
C_MON_AXI_S_TUSER_TRACE
(0: Do Not Store, 1: Store)
System Specified AXI Implemented Parameters
Device family
C_FAMILY
virtex6, spartan6
Device/part
C_DEVICE
Device package
C_PACKAGE
Device speed grade
C_SPEEDGRADE
(-1, -2, -3)
AXI memory map BUSIF name C_MON_AXI_PROTOCOL
axi4, axi4-lite, axi3
AXI stream BUSIF name
C_MON_AXI_S_PROTOCOL
System supports threads
C_MON_AXI_SUPPORTS_
THREADS
(0,1)
AXI memory map ID width
C_MON_AXI_ID_WIDTH
AXI stream ID width
C_MON_AXI_S_TID_WIDTH
AXI memory map address
width
C_MON_AXI_ADDR_WIDTH
32
AXI stream TDEST width
C_MON_AXI_S_TDEST_WIDTH
(0:32)
AXI4 memory map data width C_MON_AXI_DATA_WIDTH
(32, 64, 128, 256, 512,
1024)
AXI stream data width
C_MON_AXI_S_TDATA_WIDTH
(32, 64, 128, 256)
Default
Values
1
1
1
1
1
0
0
0
0
0
1
1
0
spartan6
xc6slx45t
fgg484
-2
axi4
generic
0
1
1
32
32
32
32
Type
string
string
string
string
string
string
string
string
string
string
string
string
string
string
string
string
string
string
string
integer
integer
integer
integer
integer
integer
integer
DS810 July 25, 2012
www.xilinx.com
11
Product Specification