DS810 Datasheet, PDF (1/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI
Monitor (v3.05.a)
DS810 July 25, 2012
Product Specification
Introduction
The ChipScope™ AXI Monitor core is designed to
monitor and debug AXI interfaces. The core allows the
probing of any signals going from a peripheral to the
AXI interconnect. For example, the user can instantiate
a monitor on a MicroBlaze™ processor instruction or
data interface to observe all memory transactions going
in and out of the processor.
Each monitor core works independently which allows
the changing of trigger outputs to enable taking
system-level measurements. By using the auxiliary
trigger input and trigger output ports of a monitor core,
multi-level triggering situations can be created to
simplify complex system level measurements. For
example, if a system consists of a master device
operating at 100 MHz and a slave device operating at 50
MHz, the transfer of data going from one time domain
to the next can be analyzed with the multi-tiered
triggering functionality of monitor cores.
Moreover, with this system level measurement, not
only can complex multi-time domain system level
issues be debugged, but latency restrictions in a system
can be analyzed as well.
Features
• Selectable data samples
• Generic Trigger/Data Unit with selectable width
• Auto-generated CDC file
• Multiple monitor support in single system through
the use of trigger in and trigger out ports
• Allows multiple match units per trigger group
• Added functionality for more than one match unit
per trigger group
• Adjustable counter size for triggers
• Selectable AXI Protocol Check monitoring for the
AXI4 Memory Map and AXI4-Lite interfaces
• Supports connection to AXI3 Protocol Cores
• Supports EDK and standard CORE Generator
flows
LogiCORE IP Facts Table
Core Specifics
Supported Device
Family⁽¹⁾
Zynq ™-7000⁽²⁾, Virtex^®-7, Kintex™-7⁽⁷⁾,
Virtex-6⁽⁴⁾, Spartan^®-6⁽⁵⁾
Supported User
Interfaces
AXI4, AXI4-Lite, AXI4-Stream
Configuration⁽⁶⁾
1
2
3
4
5
6
Resources Used
LUTs
729
1099
865
730
1252
853
Flip Flops
1141
1451
1360
1155
1663
1369
BRAMs
9
12
14
5
6
7
Documentation
Design Files
Provided with Core
Product Specification; UG029 ChipScope Pro
Software and Cores User Guide;
ISE: VHDL
Example Design
Test Bench
Constraints File
Simulation Model
Design Entry
Tools
Simulation
Tested Design Tools ⁽³⁾
Not Provided
Not Provided
Not Provided
N/A
EDK, CORE Generator
N/A
Synthesis Tools
Xilinx Synthesis Technology (XST)
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a list of supported derivative devices, see
http://www.xilinx.com/ise/embedded/ddsupport.htm.
2. Supported in ISE Design Suite implementations only.
3. For the supported versions of the tools, see the ISE Design Suite
14: Release Notes Guide.
4. For more information on the Virtex-6 devices, see the DS150,
Virtex-6 Family Overview.
5. For more information on the Spartan-6 devices, see the DS160,
Spartan-6 Family Overview.
6. For configuration details, see Table 4.
7. For more information, see DS180, 7 Series FPGAs Overview.
© Copyright 2010-2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of
Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
DS810 July 25, 2012
www.xilinx.com
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Product Specification