DS810 Datasheet, PDF (17/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 3: AXI Protocol Checks and Descriptions (Cont’d)
Name of Protocol Check
Enabling Parameter
AXI4_ERRS_RDATA_NUM
C_AXI_PC_EN_COMPLEX_CHECKS
AXI4_ERRS_RID
C_AXI_PC_EN_COMPLEX_CHECKS
AXI4_ERRM_AWVALID_RESET
C_AXI_PC_EN_RESET_CHECKS
AXI4_ERRM_WVALID_RESET
C_AXI_PC_EN_RESET_CHECKS
AXI4_ERRS_BVALID_RESET
C_AXI_PC_EN_RESET_CHECKS
AXI4_ERRM_ARVALID_RESET
C_AXI_PC_EN_RESET_CHECKS
AXI4_ERRS_RVALID_RESET
AXI4_ERRM_AWUSER_TIEOFF
AXI4_ERRM_WUSER_TIEOFF
AXI4_ERRS_BUSER_TIEOFF
AXI4_ERRM_ARUSER_TIEOFF
AXI4_ERRS_RUSER_TIEOFF
AXI4_ERRM_AWID_TIEOFF
AXI4_ERRS_BID_TIEOFF
AXI4_ERRM_ARID_TIEOFF
AXI4_ERRS_RID_TIEOFF
AXI4_AUXM_EXCL_OVERFLOW
C_AXI_PC_EN_RESET_CHECKS
(Removed)
(Removed)
(Removed)
(Removed)
(Removed)
(Removed)
(Removed)
(Removed)
(Removed)
C_AXI_PC_EN_AUX_CHECKS
AXI4_AUXM_RCAM_OVERFLOW
AXI4_AUXM_RCAM_UNDERFLOW
AXI4_AUXM_WCAM_OVERFLOW
AXI4_AUXM_WCAM_UNDERFLOW
AXI4LITE_AUXM_DATA_WIDTH
AXI4LITE_ERRS_BRESP_EXOKAY
C_AXI_PC_EN_AUX_CHECKS
C_AXI_PC_EN_AUX_CHECKS
C_AXI_PC_EN_AUX_CHECKS
C_AXI_PC_EN_AUX_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
AXI4LITE_ERRS_RRESP_EXOKAY C_AXI_PC_EN_ILLEGAL_VALUE_CHECKS
Description
The number of read data items must match
the corresponding ARLEN.
The read data must always follow the
address that it relates to. Therefore, a slave
can only give read data with an ID to match
an outstanding read transaction.
AWVALID is LOW for the first cycle after
ARESETn goes HIGH.
WVALID is LOW for the first cycle after
ARESETn goes HIGH.
BVALID is LOW for the first cycle after
ARESETn goes HIGH.
ARVALID is LOW for the first cycle after
ARESETn goes HIGH.
RVALID is LOW for the first cycle after
ARESETn goes HIGH.
Exclusive access monitor overflow, increase
EXMON_WIDTH parameter
Read CAM overflow, increase
MAXRBURSTS parameter
Read CAM underflow
Write CAM overflow, increase
MAXWBURSTS parameter
Write CAM underflow
DATA_WIDTH parameter is 32 or 64
A slave must not give an EXOKAY response
on an AXI4-Lite interface
A slave must not give an EXOKAY response
on an AXI4-Lite interface
Getting Started Tutorial
The following is a tutorial guide to design a hardware system in Xilinx Platform Studio (XPS) containing the
ChipScope AXI Monitor for capturing the signals of an AXI interface in the system. This tutorial includes basic steps
to create a software application to run on the hardware system to generate AXI traffic for the Chipscope AXI
DS810 July 25, 2012
www.xilinx.com
17
Product Specification