DS810 Datasheet, PDF (5/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 1: I/O Signal Description (Cont’d)
Signal Name
Interface
Signal Type
Init
Status
Description
MON_AXI_ARBURST(1:0)
AXI4
I
Read address burst type
MON_AXI_ARLOCK
AXI4
I
Read address lock type
MON_AXI_ARCACHE(3:0)
AXI4
I
Read address cache type
MON_AXI_ARPROT(2:0)
AXI4
I
Read address protection type
MON_AXI_ARQOS(3:0)
AXI4
I
Read address channel quality of
service
MON_AXI_ARREGION(3:0)
AXI4
I
Selects address range within multirange slave
MON_AXI_ARVALID
AXI4
I
Read address valid: When HIGH this signal
indicates the read address and control
information is valid and will remain valid until
MON_AXI_ARREADY is HIGH
1 = Address and control information valid
0= Address and control information not valid
MON_AXI_ARREADY
AXI4
I
Address ready: Indicates the slave is ready to
accept an address and associated control signals
MON_AXI_ARUSER
AXI4
I
Read address channel USER signals
MON_AXI_RID(C_MON_AXI_
ID_WIDTH-1:0)
AXI4
I
Read data ID
MON_AXI_RDATA(C_MON_
AXI_DATA_WIDTH-1:0)
AXI4
I
Read data bus
MON_AXI_RRESP(1:0)
AXI4
I
Read response: Indicates the status of the read
transaction.
MON_AXI_RLAST
AXI4
I
Read last: Indicates last read data word
MON_AXI_RVALID
AXI4
I
Read data valid: Indicates the read data is
available and the read transfer can complete
1 = read data available
0 = read data not available
MON_AXI_RREADY
AXI4
I
Read ready: Indicates the master can accept the
read data and response information
1 = master ready
0 = master not ready
MON_AXI_RUSER
AXI4
I
Read data channel USER signals
AXI4-Stream Signals
MON_AXI_S_TVALID
AXI4-Stream
I
AXI4-Stream valid
MON_AXI_S_TREADY
AXI4-Stream
I
AXI4-Stream ready
MON_AXI_S_TDATA(C_MON_
AXI_S_TDATA_WIDTH-1:0)
AXI4-Stream
I
AXI4-Stream data bus
MON_AXI_S_TKEEP(C_MON_
AXI_S_TDATA_WIDTH/8-1:0)
AXI4-Stream
I
AXI4-Stream byte qualifier
MON_AXI_S_TLAST
AXI4-Stream
I
AXI4-Stream last word
MON_AXI_S_TID(C_MON_AXI
_S_TID_WIDTH-1:0)
AXI4-Stream
I
AXI4-Stream ID
MON_AXI_S_TDEST(C_MON_
AXI_S_TDEST_WIDTH-1:0)
AXI4-Stream
I
AXI-Stream destination
DS810 July 25, 2012
www.xilinx.com
5
Product Specification