DS810 Datasheet, PDF (16/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 3: AXI Protocol Checks and Descriptions (Cont’d)
Name of Protocol Check
Enabling Parameter
AXI4_ERRS_BRESP_EXOKAY
C_AXI_PC_EN_EXCLUSIVE_CHECKS
AXI4_ERRM_ARLEN_LOCK
C_AXI_PC_EN_EXCLUSIVE_CHECKS
AXI4_ERRS_RRESP_EXOKAY
C_AXI_PC_EN_EXCLUSIVE_CHECKS
AXI4_ERRM_EXCL_ALIGN
C_AXI_PC_EN_EXCLUSIVE_CHECKS
AXI4_ERRM_EXCL_LEN
C_AXI_PC_EN_EXCLUSIVE_CHECKS
AXI4_RECM_EXCL_MATCH
C_AXI_PC_EN_EXCLUSIVE_CHECKS
AXI4_ERRM_EXCL_MAX
AXI4_RECM_EXCL_PAIR
C_AXI_PC_EN_EXCLUSIVE_CHECKS
C_AXI_PC_EN_EXCLUSIVE_CHECKS&
C_AXI_PC_EN_ARM_REC_ONLY_CHECKS
AXI4_RECS_AWREADY_MAX_WAIT C_AXI_PC_EN_ARM_REC_WAIT_CHECKS
AXI4_RECS_WREADY_MAX_WAIT C_AXI_PC_EN_ARM_REC_WAIT_CHECKS
AXI4_RECM_BREADY_MAX_WAIT C_AXI_PC_EN_ARM_REC_WAIT_CHECKS
AXI4_RECS_ARREADY_MAX_WAIT C_AXI_PC_EN_ARM_REC_WAIT_CHECKS
AXI4_RECM_RREADY_MAX_WAIT C_AXI_PC_EN_ARM_REC_WAIT_CHECKS
AXI4_ERRM_WDATA_NUM
C_AXI_PC_EN_COMPLEX_CHECKS
AXI4_ERRS_BRESP_WLAST
AXI4_ERRS_BRESP_AW
C_AXI_PC_EN_COMPLEX_CHECKS
C_AXI_PC_EN_COMPLEX_CHECKS
Description
An EXOKAY write response can only be
given to an exclusive write access
Exclusive access transactions cannot have
a length greater than 16 beats
An EXOKAY write response can only be
given to an exclusive read access
The address of an exclusive access is
aligned to the total number of bytes in the
transaction
The number of bytes to be transferred in an
exclusive access burst is a power of 2, that
is, 1, 2, 4, 8, 16, 32, 64, or 128 bytes
Recommended that the address, size, and
length of an exclusive write with a given ID is
the same as the address, size, and length of
the preceding exclusive read with the same
ID
128 is the maximum number of bytes that
can be transferred in an exclusive burst
Recommended that every exclusive write
has an earlier outstanding exclusive read
with the same ID
Recommended that AWREADY is asserted
within MAXWAITS cycles of AWVALID being
asserted.
Recommended that WREADY is asserted
within MAXWAITS cycles of WVALID being
asserted.
Recommended that BREADY is asserted
within MAXWAITS cycles of BVALID being
asserted.
Recommended that ARREADY is asserted
within MAXWAITS cycles of ARVALID being
asserted.
Recommended that RREADY is asserted
within MAXWAITS cycles of RVALID being
asserted.
The number of write data items matches
AWLEN for the corresponding address. This
is triggered when any of the following
occurs:
• write data arrives and WLAST is set, and
the WDATA count is not equal to AWLEN
• write data arrives and WLAST is not set,
and the WDATA count is equal to AWLEN
• ADDR arrives, WLAST is already
received, and the WDATA count is not
equal to AWLEN.
(Removed)
A slave must not take BVALID HIGH until
after the write address is handshaken
DS810 July 25, 2012
www.xilinx.com
16
Product Specification