DS810 Datasheet, PDF (20/21 Pages) Xilinx, Inc – LogiCORE IP ChipScope AXI

LogiCORE IP ChipScope AXI Monitor (v3.05.a)
Table 4: Configuration Details
Configuration
Device
1
xc6slx45t-fgg484-3
2
xc6slx45t-fgg484-3
3
xc6slx45t-fgg484-3
4
xc6vlx240t-ff1156-1
5
xc6vlx240t-ff1156-1
6
xc6vlx240t-ff1156-1
System Setup
ChipScope AXI Monitor enabled; AXI Protocol Checker
disabled; AXI4 Memory Map; 10 trigger groups enabled;
Data Width of 32; Sample depth of 1024
ChipScope AXI Monitor enabled; AXI Protocol Checker with
50% of checks enabled; AXI4 Memory Map; 10 trigger
groups enabled; Data Width of 32; Sample depth of 1024
ChipScope AXI Monitor enabled; AXI Protocol Checker with
100% of checks enabled; AXI4 Memory Map; 10 trigger
groups enabled; Data Width of 32; Sample depth of 1024
ChipScope AXI Monitor enabled; AXI Protocol Checker
disabled; AXI4 Memory Map; 10 trigger groups enabled;
Data Width of 32; Sample depth of 1024
ChipScope AXI Monitor enabled; AXI Protocol Checker with
50% of checks enabled; AXI4 Memory Map; 10 trigger
groups enabled; Data Width of 32; Sample depth of 1024
ChipScope AXI Monitor enabled; AXI Protocol Checker with
100% of checks enabled; AXI4 Memory Map; 10 trigger
groups enabled; Data Width of 32; Sample depth of 1024
References
• More information on the ChipScope Pro software and cores is available in the Software and Cores User Guide,
located at http://www.xilinx.com/support/documentation.
• Information about hardware debugging using ChipScope Pro in EDK is available in the Platform Studio 12
online help, located at http://www.xilinx.com/support/documentation.
• Information about hardware debugging using ChipScope Pro in System Generator for DSP is available in the
Xilinx System Generator for DSP User Guide, located at http://www.xilinx.com/support/documentation.
Support
Xilinx provides technical support for this LogiCORE™ IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
CORE Generator Support
A stand alone core to use in non-XPS systems, Chipscope AXI Monitor IP can be generated from the
CORE Generator tool. CORE Generator supports all the parameters as supported by XPS. While generating
Chipscope AXI monitor from coregen following files are generated:
• Fully synthesized netlist
• UCF file for ILA level timing constraints
• CDC file for specific configuration
• A dummy top level synthesis model file
• Datasheet and readme documents
DS810 July 25, 2012
www.xilinx.com
20
Product Specification