W25Q256JVEIQ-TR Datasheet, PDF (9/92 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI

W25Q256JV
3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Figure 1c. W25Q256JV Ball Assignments, 24-ball TFBGA 6x8-mm (Package Code B & C)
3.6 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
A4
/RESET
I
Reset Input⁽³⁾
B2
CLK
I
Serial Clock Input
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
Chip Select Input
C4
IO2
I/O
Data Input Output 2⁽²⁾
D2
DO (IO1)
I/O Data Output (Data Input Output 1)⁽¹⁾
D3
DI (IO0)
I/O
Data Input (Data Input Output 0)⁽¹⁾
D4
IO3
I/O
Data Input Output 3⁽²⁾
Multiple
NC
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions (factory default for Quad Enabled part numbers with ordering option “IQ”).
3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset
function is not used, this pin can be left floating or connected to VCC in the system
Publication Release Date: September 20, 2016
-8-
Revision B