W25Q256JVEIQ-TR Datasheet, PDF (44/92 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI

W25Q256JV
8.2.16 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status
Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast
Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24/32-bit
address as shown in Figure 21. The dummy clocks allow the device's internal circuits additional time for
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock.
/CS
CLK
IO₀
IO₁
IO₂
IO₃
/CS
CLK
IO₀
IO₁
IO₂
IO₃
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (6Bh)
24-Bit Address
23 22 21
* _{High Impedance}
3210
High Impedance
High Impedance
* ^{= MSB}
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
0
High Impedance
High Impedance
High Impedance
IO₀ switches from
Input to Output
404040404
515151515
626262626
737373737
Byte 1 Byte 2 Byte 3 Byte 4
Figure 21. Fast Read Quad Output Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
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