W25Q256JVEIQ-TR Datasheet, PDF (17/92 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI

W25Q256JV
7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) – Volatile/Non-Volatile Writable
The Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register (S5, S4,
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can
be protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP3, BP2, BP1, BP0) protect from
the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection
table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the WEL bits.
7.1.5 Complement Protect (CMP) – Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with TB, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by TB, BP3, BP2, BP1 and BP0 will be reversed. For
instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when
CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please
refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
7.1.6 Status Register Protect (SRL) – Volatile/Non-Volatile Writable
The Status Register Lock bit (SRL) is a volatile/non-volatile read/write bit in the status register (S8). The
SRL bit controls the method of write protection to the Status Registers: temporary Power Lock-Down or
permanently One Time Program OTP.
SRL
0
1
Status Register Lock
Description
Non-Lock
Status Register is unlocked
Lock-Down ⁽¹⁾
(temporary/Volatile)
Status Register is locked by standard status register
write command and can’t be written to again until the
next power-down, power-up cycle.
One Time Program⁽²⁾
Status Register is permanently locked by special
(Permanently/Non-Volatile) command flow* and can’t be written to
1. When SRL =1 , a power-down, power-up cycle will change SRL =0 state.
2. Please contact Winbond for details.
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Publication Release Date: September 20, 2016
Revision B