W25Q256JVEIQ-TR Datasheet, PDF (3/92 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI

W25Q256JV
7.1.12 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable .....................................18
7.1.13 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable .........................19
7.1.14 Reserved Bits – Non Functional......................................................................................19
7.1.15 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 0).............................20
7.1.16 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 1).............................21
7.1.17 W25Q256JV Individual Block Memory Protection (WPS=1) ..............................................22
7.2 Extended Address Register – Volatile Writable Only ...................................................... 23
8. INSTRUCTIONS ............................................................................................................................. 24
8.1 Device ID and Instruction Set Tables ................................................................................. 24
8.1.1 Manufacturer and Device Identification ................................................................................24
8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte Address Mode)⁽¹⁾ .......................25
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode) .......................26
8.1.4 Instruction Set Table 3 (Standard SPI, 4-Byte Address Mode)⁽¹⁾..........................................27
8.1.5 Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode) ......................28
8.2 Instruction Descriptions ...................................................................................................... 30
8.2.1 Write Enable (06h) ...............................................................................................................30
8.2.2 Write Enable for Volatile Status Register (50h) ....................................................................30
8.2.3 Write Disable (04h)...............................................................................................................31
Figure 7. Write Disable Instruction for SPI Mode..............................................................................31
8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) ..............31
8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) ..............32
8.2.6 Read Extended Address Register (C8h) ..............................................................................34
8.2.7 Write Extended Address Register (C5h) ..............................................................................35
8.2.8 Enter 4-Byte Address Mode (B7h)........................................................................................36
8.2.9 Exit 4-Byte Address Mode (E9h) ..........................................................................................36
8.2.10 Read Data (03h) .................................................................................................................37
8.2.11 Read Data with 4-Byte Address (13h) ................................................................................38
8.2.12 Fast Read (0Bh) .................................................................................................................39
8.2.13 Fast Read with 4-Byte Address (0Ch) ................................................................................40
8.2.14 Fast Read Dual Output (3Bh) .............................................................................................41
8.2.15 Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................42
8.2.16 Fast Read Quad Output (6Bh)............................................................................................43
8.2.17 Fast Read Quad Output with 4-Byte Address (6Ch)...........................................................44
8.2.18 Fast Read Dual I/O (BBh)...................................................................................................45
8.2.19 Fast Read Dual I/O with 4-Byte Address (BCh)..................................................................46
8.2.20 Fast Read Quad I/O (EBh) .................................................................................................47
8.2.21 Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................48
8.2.22 Set Burst with Wrap (77h) ..................................................................................................49
8.2.23 Page Program (02h) ...........................................................................................................50
8.2.24 Page Program with 4-Byte Address (12h) ..........................................................................51
8.2.25 Quad Input Page Program (32h) ........................................................................................52
8.2.26 Quad Input Page Program with 4-Byte Address (34h) .......................................................53
Publication Release Date: September 20, 2016
-2-
Revision B