W25Q256JVEIQ-TR Datasheet, PDF (46/92 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI

W25Q256JV
8.2.18 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23/A31-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Similar to the Fast Read Dual Output (3Bh) instruction, the Fast Read Dual I/O instruction can operate at
the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
four “dummy” clocks after the 24/32-bit address as shown in Figure 23. The dummy clocks allow the
device's internal circuits additional time for setting up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first
data out clock.
/CS
CLK
Mode 3
Mode 0
DI
(IO₀)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
DO
(IO₁)
/CS
CLK
DI
(IO₀)
* ^{= MSB}
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
*
*
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
IOs switch from
Input to Output
064206420642064206
DO
(IO₁)
175317531753175317
* Byte 1
* Byte 2
* Byte 3
* Byte 4
Figure 23a. Fast Read Dual I/O (M7-M0 should be set to FFh)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
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