W25Q256JVEIQ-TR Datasheet, PDF (25/92 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI

W25Q256JV
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25Q256JV consists of 48 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1-4). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5
through 57. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent
writes. Additionally, while the memory is being programmed or erased, or when the Status Register is
being written, all instructions except for Read Status Register will be ignored until the program or erase
cycle has completed.
8.1 Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID
Winbond Serial Flash
(MF7 - MF0)
EFh
Device ID
Instruction
W25Q256JV
(ID7 - ID0)
ABh, 90h, 92h, 94h
18h
(ID15 - ID0)
9Fh
4019h
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Publication Release Date: September 20, 2016
Revision B