W83L951DG Datasheet, PDF (76/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
6.10 UART Block
W83L951DG/FG supports one Universal asynchronous serial I/O mode (UART) .Eight serial data
transfer formats can be selected, for vary selection of Stop bit, Parity, Parity check, Data length, and
the transfer formats used by a transmitter and receiver must be identical.
The transmitter and receiver shift registers each have a buffer, but the two buffers have the same
address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read from the receive buffer register. The
transmit buffer register can also hold the next data to be transmitted, and the receive buffer register
can hold a byte while the next byte is being received.
Table 6-18.UART Register Define
UART Block(5)
ExtAddr Name
7
6
5
4
3
2
1
0
30
UARTCON TxEn TS
RxEn PARE PARS STPS CHAS Reserved
31
UARTSTS ParErr FrameErr OverErr Reserved
RxBFull TxBFull
32
BRGH
Baud Rate Generator High Byte[7:0]
33
BRGL
Baud Rate Generator Low Byte[7:0]
34
UARTBUF UART Transmit / Receive Buffer[7:0]
Gray: Only with System Reset to initial.
6.10.1 Register Description
6.10.1.1 UART Control Register (UARTCON) (Default Value: 0000_0000)
Bit 7: Transmit enable bit (TE)
0: Transmit disabled. 1: Transmit enable.
Bit 6: Transmit Speed up bit (TS) (Reserved)
0: Disable.
1: Enable.
Bit 5: Receive enable bit (RE)
0: Receive disable. 1: Receive enable.
Bit 4: Parity enable bit (PARE).
0: Parity Bit disable. 1: Parity Bit enable.
Bit 3: Parity selection bit (PARS).
0: Odd parity. 1: Even parity.
Bit 2: Stop bit length selection bit (STPS)
0: 1 stop bit. 1: 2 stop bits.
- 72 -