W83L951DG Datasheet, PDF (45/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
Bit4: Port 92 Enable (Default Value: 0)
1: Enable W83L951DG/FG’s hardware logic to receive the data written in I/O address@0092h. Bit1
and bit0 of port92 control register controls Gate A20 and KBRST pin. Gate A20 will drive high
when bit1 is 1 and KBRESET pin drive {14us High → 6us Low → High} waveform when bit0 is 1.
Gate A20 is default high level after LPC reset and GP44, GP45 GPIO function is disabled.
0: Disable
Bit3: Hardware Keyboard Reset Control Enable (Default Value: 0)
1: Enable W83L951DG/FG’s hardware logic to set KBRESET. When the KBC receives data that
follows a “FE” command, the KBRESET pin drives {14us High → 6us Low → High} waveform. And
GP44 GPIO function is disabled.
0: Disable
Bit2: Hardware Gate A20 Control Enable (Default Value: 0)
1: Enable W83L951DG/FG’s hardware logic to set Gate A20. When the KBC receives data that
follows a “D1” command, the Gate A20 pin drives high. And GP45 GPIO function is disabled.
0: Disable
Bit1: Gate A20 Set
Set directly Gate A20 Output Register. If host is setting from LPC Interface, the request will be
ignored. This belongs to software control.
Bit0: Gate A20 Clear/Gate A20 Status
Write: Clear directly Gate A20 Output Register. If host is setting from LPC Interface, the request will
be ignored. This belongs to software control.
Read: Current Internal Gate A20 Status.
6.2.1.9 DBB1 Status Register (DBB1STS) (Default Value: 0000_?0?0)
Bit7~4: User Define Flag
Bit3: Indicate IDBB Command/Data (By LRESET# Pin to reset)
1: Command, 0: Data.
Bit2: User Define Flag
Bit1: Input Buffer Full Flag (By LRESET# Pin to reset)
1: Full, 0: Empty
Bit0: Output Buffer Full Flag
1: Full, 0: Empty
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Publication Release Date: August 2006
Revision 1.0