W83L951DG Datasheet, PDF (53/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
6.4.1 Register Description
6.4.1.1 System Control Register (SM1/2SCR) (Default Value: 0001_10?0)
Bit 7~6: Reserved (Must Assign Low)
Bit 5~3: Baud Rate Select
Select SMBus baud rate.
Input Clock is 24MHz :
When System Clock is 24MHz:
000: 12.5 KHz, 001: 25 KHz, 010: 50 KHz, 011: 100 KHz
100: 400 KHz, 101: 800 KHz, 110: 1.2 MHz, 111: 2.4 MHz
When System Clock is 12MHz:
000: 12.5 KHz, 001: 25 KHz, 010: 50 KHz, 011: 100 KHz
100: 400 KHz, 101: 800 KHz, 110: 1.2 MHz, 111: N/A
When System Clock is 6MHz:
000: 12.5 KHz, 001: 25 KHz, 010: 50 KHz, 011: 100 KHz
100: 400 KHz, 101: 800 KHz, 110: N/A, 111: N/A
Input Clock is 12MHz
When System Clock is 12MHz:
000: 6.25 KHz, 001: 12.5 KHz, 010: 25 KHz, 011: 50 KHz
100: 200 KHz, 101: 400 KHz, 110: 600 KHz, 111: 1.2 MHz
When System Clock is 6MHz:
000: 6.25 KHz, 001: 12.5 KHz, 010: 25 KHz, 011: 50 KHz
100: 200 KHz, 101: 400 KHz, 110: 600 KHz, 111: N/A
When System Clock is 3MHz:
000: 6.25 KHz, 001: 12.5 KHz, 010: 25 KHz, 011: 50 KHz
100: 200 KHz, 101: 400 KHz, 110: N/A, 111: N/A
Bit 2: Rx Byte Interrupt Mode
Select the mode that SMBus receive data bytes to generate Master/Slave Data Ready interrupt.
0: Only First Byte and FIFO Full Byte:
Master/Slave Data Ready Interrupt only occurs in receiving first byte after Start phase or
Repeat_Start phase and any byte that make FIFO enter Full state.
1: Every Byte:
Master/Slave Data Ready Interrupt occurs in every time to finish receiving one byte.
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Publication Release Date: August 2006
Revision 1.0