W83L951DG Datasheet, PDF (57/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
6.5 Internal Interrupt Controller Block
W83L951DG/FG Interrupts occur by 28 sources, 27 external and 25 internal interrupt.
About Interrupt Control, each interrupt is controlled and corresponding to a bit in Interrupt Enable
Register (IE1/2/3/4), the Interrupt Priority Control Register (IP1/2/3/4) and the Interrupt Request
Register (IREQ1/2/3/4).
An interrupt occurs if the corresponding Interrupt Request occurs and enable bits is HIGH. When
several interrupts occur at the same time, the interrupts are received according to priority setting. If
interrupts are setting to same priority, then it is decided by hardware internal checking rule.
After Interrupt of EXTINT1, EXTINT2, EXTINT3, SMBUS1, SMBUS2, FAN1 and FAN2 is produced,
can't be interrupt by other Interrupt source, so should set as High Propriety.
Table 6-11 Internal Interrupt Controller Register Define
INTERRUPT BLOCK(17)
INTADDR NAME
7
6
5
4
3
2
1
0
E1
IE1
TimerY TimerX Timer2 Timer1 OBE1 IBF1
OBE0
IBF0
E2
IE2
CNTR1 CNTR0 ADC
RTC
KEY-
WP
EXINT3 EXTINT2 EXTINT1
E3
IE3
FAN2 FAN1 CIR
APS2 MPS2 KPS2 SMBUS2 SMBUS1
E4
IE4 R
R
R
R
R
R
UARTRX UARTTX
E9
IREQ1 TimerY TimerX Timer2 Timer1 OBE1 IBF1 OBE0 IBF0
EA
IREQ2 CNTR1 CNTR0 ADC
RTC
KEY-
WP
EXINT3 EXTINT2 EXTINT1
EB
IREQ3 FAN2 FAN1 CIR APS2 MPS2 KPS2 SMBUS2 SMBUS1
EC
IREQ4 R
R
R
R
R
R
UARTRX UARTTX
F1
IPRO1 TimerY TimerX Timer2 Timer1 OBE1 IBF1 OBE0 IBF0
F2
IPRO2 CNTR1 CNTR0 ADC
RTC
KEY-
WP
EXINT3 EXTINT2 EXTINT1
F3
IPRO3 FAN2 FAN1 CIR APS2 MPS2 KPS2 SMBUS2 SMBUS1
F4
IPRO4 R
R
R
R
R
R
UARTRX UARTTX
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Publication Release Date: August 2006
Revision 1.0