W83L951DG Datasheet, PDF (56/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
Bit 5: Master Almost Full Event
Indicate that Master generate Almost Full Event. It occurs only up to Almost Full level.
Bit 4: Master Almost Empty Event
Indicate that Master generate Almost Empty Event. It occurs only down to Almost Empty level.
Bit 3: Master FIFO Data Write Error Event
Indicate that Microprocessor writes to Master FIFO, Master FIFO is full or Read Mode.
Bit 2: NACK Received Event
Indicate that Master receives NACK. After generating Stop Phase, Master will be back to initial state
and clear FIFO.
Note: Wait for the response of Clear Finished Event in Master Status Register to start next
transfer.
Bit 1: Bus Arbitration Failed Event
Indicate that bus arbitration failed. Master will be back to initial state and clear FIFO.
Bit 0: FIFO Clear Finished Event
Indicate that Master finishes the request to clear FIFO.
Note: When Micro Processors has not proposed Master FIFO Clear Request but produces, it
indicates the remote device to drive SCL low to generate timeout.
6.4.1.8 Master FIFO Status Register (SM1/2MFIFOSTS) (Default Value: 0100_0000)
Bit 7: Full Flag
Bit 6: Empty Flag
Bit 5~4: Reserved
Bit 3~0: FIFO Data Length
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