W83L951DG Datasheet, PDF (111/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
11. DEMO CIRCUITS
Matrix_Column[19..0]
Matrix Keyboard Row
Input Pull-High
VCC1
KR7
KR6
KR5
KR4
RP1
1
8
2
7
3
6
4
5
4.7K
Matrix Keyboard
You can select 8x16 or 8x20
matrix keyboard.
Pin73~77 can be KC16~19 of
8x20 matrix keyboard or
GPIO20~23.
KR3
KR2
KR1
KR0
RP2
1
8
2
7
3
6
4
5
Mat rix _R ow[ 7. . 0]
4.7K
Remark: GP30~GP37(pin95~pin102) should to
pull up VCC . If design for S3,S5 wake up by
matrix keyboard, please pull up to standby
VCC.
KC19
KC18
KC17
KC16
KC15
KC14
KC13
KC12
KC11
KC10
KC9
KC8
KC7
KC6
KC5
KC4
KC3
KC2
KC1
KC0
KR7
KR6
System Clock
Q1
24MHZ
1M R16
C3
22P
XOUT
XIN
C4
22P
RTC Clock
Q2
XCOUT
XCIN
32.768KHZ
R2
C7 10M~20M
C8
22P
22P
VREF
AVCC
KR5 97
KR4 98
KR3 99
KR2 100
KR1 101
KR0 102
103
AD7
AD AD6
AD5
104
105
106
107
AD4
AD3
AD2
108
109
110
AD1
111
AD0
112
DA2
DA DA1
113
114
115
GP55
GP54
GP53
GP52
GP51
116
117
118
119
120
121
GP50
XOUT
XI N
122
123
124
TEST#
XCOUT
XCIN
GPC7
GPC6
125
126
127
128
GP35/M_KR5/FPEN#
GP34/M_KR4/FLATCH
GP33/M_KR3/FCTRL3
GP32/M_KR2/FCTRL2
GP31/M_KR1/FCTRL1
GP30/M_KR0/FCTRL0
VREF
AD7/GP67
AD6/GP66
AD5/GP65
AD4/GP64
AD3/GP63
AD2/GP62
AD1/GP61
AD0/GP60
AVCC
DA2/GP57
DA1/GP56
AGND
GP55
GP54
GP53
GP52
GP51
GP50
XOUT
XIN
TEST#
XCOUT
XC I N
EXTI N T37/ GPC 7
EXTI N T36/ GPC 6
VCC1 and VCC2:
VCC1 is W83L951D normal power input, it can be 3.3VCC
or 3.3VSB or 3.3Vbat based on customer's design.
VCC2 is power status that indicates power status of LPC
interface. Please connect it to 3.3VCC from LPC
interface.
GPC5
GPC4
GPC3
GPC2
GPC1
GPC0
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
W83L951D
VCC1
C1 C2
0.1U 10U
UART for Debug
For Firmware debug , suggest to keep
the Pin65,Pin66 to UART function , and
add test point for using.
PWM0
PWM1
PWM2
PWM3
FAN0
FAN1
RXD
TXD
U1
PWM
Fan Tachometer
UART
VCC2
64
GP44/KBRST# ₆₃
GP45/GATE_A20
GP46/CLKRUN#
GP47
VCC2
62
61
60
59
LAD3
LAD2
LAD1
LAD0
GND
58
57
56
55
54
SERIRQ
LRESET#
LFRAME#
53
52
51
LCLK ₅₀
RESET#
VCC1
GP70/PS2_1CLK
GP71/PS2_1DAT
GP72/PS2_2CLK
GP73/PS2_2DAT
GP74/PS2_3CLK
GP75/PS2_3DAT
GP76/SDA0
GP77/SCL0
49
48
47
46
45
44
43
42
41
40
GP80/SDA1
GP81/SCL1
CNTR0/GP82
39
38
37
CNTR1/GP83
CIR_RX/GP84
GP85
GP86
GP87
36
35
34
33
KBRST#
GATE_A20
CLKRUN#
LPCPD#
R17
4.7K
LAD3
LAD2 LPC Interface
LAD1
LAD0
SERIRQ
LRESET#
LFRARM4 E# ₃₃
R5
0
PCICLK
RESET#
VCC1
PS2_1CLK
PS2_1DAT
PS2_2CLK
C5
C6
10U
0.1U
PS2_2DAT
PS2_3CLK PS2 Interface
PS2_3DAT
SDA0
SCL0
SDA1 SMBUS
SCL1
CNTR0
CNTR1
CIR_RX CIR Receiver
GP85
GP86
GP87
RXD
TXD
JP1
1
2
HEADER 2
951_Flash Switch
VCC1
R1
10K
RESET#
C11
1U
J P2
1
2
HEADER 2
VCC1
TEST#
R3
4.7K
JP3
1
2
HEADER 2
TEST# RESET# Chip Status
0
0 Internal flash access enable
Normal operation by direct
0
1 external rom
1
0 Normal reset
1
1 Normal operation
PS2 Interface and SMBUS Pull-high
Please select 3.3V or 5V pull-high
based on your request in PS2
device.
VCC1
VCC1
W83L951D
GP90
GP91
GP92
GP93
GP94
GP95
GP96
GP97
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
VCC1
C9 C10
10U 0.1U
PS2_1CLK
PS2_1DAT
PS2_2CLK
PS2_2DAT
PS2_3CLK
PS2_3DAT
SDA0
SCL0
SDA1
SCL1
R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
Winbond Electronic Corp.
Title
W83L951D SCHEMATIC
Size Document Number
B
<Doc>
Date:
Wednesday , June 15, 2005
Sheet
Rev
0.52
1
of 1
- 107 -
Publication Release Date: August 2006
Revision 1.0