W83L951DG Datasheet, PDF (54/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
Bit 1: SMBALERT Pin Status (Reserved)
Bit 0: SMBALTER Event Control (Reserved)
Control the occurrence of SMBALTER Event
0: Disable
1: Enable.
6.4.1.2 Interrupt Register (SM1/2IREQ) (Default Value: 0000_0000)
Bit 7: Master Status
Indicate Master Status Register changed.
Bit 6: Master FIFO Data Ready Interrupt
Indicate that FIFO finishes receiving data byte when Master is under MSR (Master at Receiving)
mode. About detail description, please refer Bit7@SM1/2SCR.
Bit 5: Master FIFO Data Request Interrupt
Indicate that FIFO request micro-processor provides data for transmitting to Salve when Master is
under MST (Master at Transmitting) mode and empty.
Bit 4: Master Packet Finished Interrupt
Indicate that Master finishes package transmission (Include Rx and Tx).
Bit 3~0: Reserved
6.4.1.3 Interrupt Enable Register (SM1/2IE) (Default Value: 0000_0000)
All Bits:
1: Enable Interrupt.
The content of Interrupt Register via OR operation will convert into Microprocessor Internal Interrupt
Source.
0: Disable Interrupt.
Disable convert into Microprocessor Internal Interrupt, but relative interrupt flag will still be produced.
6.4.1.4 FIFO Control Register (SM1/2FIFOCON) (Default Value: 0000_0000)
Bit 7: STOP Tag Flag (Only for Master)
Indicate that writing byte is the last byte.
Bit 6: Repeat_Start Tag Flag (Only for Master)
Indicate that writing byte is Repeat_Start Byte.
Bit 5~4: Master FIFO Threshold Level Select
00: AE – 2, AF – 6, 01: AE - 3, AF – 5
10: AE – 4, AF – 4, 11: Disable
Note: AE is Almost Empty Flag, AF is Almost Full Flag.
- 50 -