W83L951DG Datasheet, PDF (71/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
Operating on event counter mode is the almost same as in timer mode, except that the timer counts
signals input through the CNTR1. When the CNTR1 active edge selection bit is 0, the rising edge on
the CNTR1 pin is counted. When the CNTR1 active edge selection bit is 1, the falling edge on the
CNTR1 pin is counted.
11: Pulse width measurement mode (Disable GP83 Function, Direct Force “Input”)
If the CNTR1 active edge selection bit is 0, the timer counts XlN/16 while the CNTR1 pin is H. If the
CNTR1 active edge selection bit is 1, the timer counts while the CNTR1 pin is ‘L’.
Bit 3: Timer X Start Bit
1: Enable (Prescale X & Timer X Data Keep)
0: Disable
Bit 2: CNTR0 active edge selection bit
0: Interrupt at falling edge Count at rising edge in event counter mode.
1: Interrupt at rising edge Count at falling edge in event counter mode.
Bit 1-0: Timer X operating bit
00: Timer mode
The Timer X only counts XIN/16.
01: Pulse output mode (Disable GP82 Function, Direct Force “Output”)
Timer X counts XIN/16. Whenever the contents of the timer reach “00H”, the signal output from the
CNTR0 pin is inverted. If the CNTR0 active edge selection bit is 0, the pin is “H” after initial. If it is 1,
the pin is ‘L’ after initial. When using a timer in this mode, set the corresponding direction register of
port GP82 to output mode.
10: Event count mode (Disable GP82 Function, Direct Force “Input”)
Operating on event counter mode is the almost same as in timer mode, except that the timer counts
signals input through the CNTR0. When the CNTR0 active edge selection bit is 0, the rising edge on
the CNTR0 pin is counted. When the CNTR0 active edge selection bit is 1, the falling edge on the
CNTR0 pin is counted.
11: Pulse width measurement mode (Disable GP82 Function, Direct Force “Input”)
If the CNTR0 active edge selection bit is 0, the timer counts XlN/16 while the CNTR0 pin is H. If the
CNTR0 active edge selection bit is 1, the timer counts while the CNTR0 pin is ‘L’.
Note: The count can be stopped by setting a “0” to the timer X (or timer Y) count start bit in
any mode. The corresponding interrupt request bit is set each time a timer underflows.
6.8.1.6 Clock Prescale Number of Timer X (PREX) (Default Value: 1111_1111)
Bit 7~0: Clock Prescale Number
Write: Prescale Counter Reload.
Read: Current Prescale Counter Value
Note: In writing, due to the effect of internal frequency XIN/16, 0~16 system clock error occurs in first
prescale period width.
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Publication Release Date: August 2006
Revision 1.0