W83L951DG Datasheet, PDF (55/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
Bit 3: Clear Master FIFO
Clear Master FIFO. Master will stop transfer immediately and generate Stop phase. After SMBus
finishes the action, SMBus responds to micro-processor via FIFO Clear Finished Event in Master
Status Register.
Bit 2~0: Reserved
6.4.1.5 Master Data FIFO Register (SM1/2MFIFO) (Default Value: 0000_0000)
This FIFO register stores the data from Master.
Only allow writing in MST mode, and only allowed to read in MSR mode. Default is MST mode and
transforming is through Data_Ready_Interrupt.
6.4.1.6 Master Control Register (SM1/2MCON) (Default Value: 0100_0000)
Bit 7: Master Enable
Bit 6: Read Mode Select
1: Host Read One Byte Hold Mode.
Master holds bus (drive SCL low) after finishing receiving every byte.
0: Host Read Continue Mode.
Master finishes {Receiving Package -> Stop Phase -> Release Bus} automatically according to read
byte count.
Note: If Read Byte Count initial value is 1, Master will ignore criterion of “Host Read One Byte
Hold Mode”.
Bit 5~0: Read Byte Count
Indicate Read Byte Count. The allowed maximum is 64 bytes block read.
Filled Value Actual Value
0
64
1~63
1~63
6.4.1.7 Master Status Register (SM1/2MSTS) (Default Value: 0000_0000)
Bit 7: Master Rx Timeout Event
Indicate Master generates RX_TIMEOUT (When Master FIFO is full, SCL drive low to generate
timeout). After the Master generates Stop Phase, will be back to initial state and clear FIFO.
Note: If timeout is not generated by the Master, the response will occur in FIFO Clear Finished
Event in Master Status Register.
Bit 6: Master Tx Timeout Event
Indicate Master generates TX_TIMEOUT (When Master FIFO is empty, SCL drive low to
timeout). After Master generates Stop Phase, will be back to initial state and clear FIFO.
generate
Note: If timeout is not generated by Master, the response is in FIFO Clear Finished Event in
Master Status Register.
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Publication Release Date: August 2006
Revision 1.0