W83L951DG Datasheet, PDF (20/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
5.3 LPC Interface Part
LPC Interface is formed by LAD0~LAD3, SERIRQ, LRESET#, LFRAME#, LCLK and VCC2. These
pins are defined by LPC interface Spec except VCC2. Below are descriptions about all LPC pins:
Table 5-4 LPC interface pin configuration table
SYMBOL
PIN
I/O
FUNCTION
LCLK
51
I_ts
PCI clock input. Same 33MHz clock as PCI clock on the host.
Same clock phase with typical PCI skew.
LFRAME#
52
LRESET#
53
SERIRQ
54
LAD0
56
I_ts
I_ts
I/O_24ts
I/O_24ts
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
Serial IRQ input/Output.
LAD[3..0] are multiplexed address, control, and data in LPC
bus.
LAD1
57
I/O_24ts
LAD[3..0] are multiplexed address, control, and data in LPC
bus.
LAD2
58
I/O_24ts
LAD[3..0] are multiplexed address, control, and data in LPC
bus.
LAD3
59
I/O_24ts
LAD[3..0] are multiplexed address, control, and data in LPC
bus.
Note: Other pins about LPC interface, CLKRUN#: Please see “GP4” part.VCC2: Please see “power & clock” part.
5.4 GPIO0 Part
This part contains:
General Purpose I/O Function
Default is General Purpose I/O. Change the value of GPIO0 and GPIOD0 register to determine 8
input/output.
Keyboard Matrix Column Output
Use Chipctrl2 register bit 3 to enable {GP0, GP1, GP20~23} keyboard scan and GP3 key wakeup
interrupt function.
Internal Flash Access Interface
When TEST# and RESET# are both low, Internal Flash Access Interface is enabled and other
functions are disabled.
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