W83L951DG Datasheet, PDF (67/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
6.7 Watch Dog Block
The watchdog timer gives a mean of returning to the reset state when a program cannot run on a
normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit
timer L and an 8-bit timer H. At reset or writing to the watchdog timer control register WDTCON [7]
(START), each watchdog timer H and L is set to 0FFh.
About Watchdog timer H count size selection, we can use Bit 5 of the watchdog timer control register
(SIZE) permits selecting a watchdog timer H count source. When this bit is set to LOW, the count
source becomes the underflow signal of watchdog timer L.
Table 6-15.Watch Dog Register Define
WATCH DOG BLOCK(1)
EXTADDR
NAME
7
6
5
00
WDTCON START INTTYPE SIZE
01
WDTSTS Reserved
4321
0
Clock Prescale Number[4:0]
+WDT
Gray: Only with System Reset (Pin Reset + WDT Reset) to Initial.
+: Only with Pin Reset to Initial
6.7.1 Register Description
6.7.1.1 Watch Dog Control Register (WDTCON) (Default Value: 0000_0000)
Reset with Power Reset & Pin Reset.
Bit 7: Start
1: Start / Reload
0: Stop
This Bit permits enable/disable the watchdog timer. Write LOW to this bit, the watchdog timer is
stopped. Write HIGH to this bit will reload the watchdog timer (watchdog timer H and L is set to 0FFh)
even this bit is already be HIGH. After written HIGH, the watchdog timer is running. Once this timer is
timed-out the chip is reset. Also the watchdog timer is stopped to prevent the next time-out.
Bit 6: Interrupt Type
1: NMI
0: Hardware reset
Bit 5: Size
Select the counter size. The counter starts from low to overflow. Then generate interrupt or hardware
reset.
1: One Byte Counter. ^{WDT Timeout Limit ≈ 256 Count Frequency} .
0: Two Byte Counter. ^{WDT Timeout Limit ≈ 65536 Count Frequency} .
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Publication Release Date: August 2006
Revision 1.0