W83L951DG Datasheet, PDF (43/112 Pages) Winbond – Mobile Keyboard and Embedded Controller

W83L951DG/W83L951FG
6.2.1.3 Data Bus Buffer 0 Address High Byte Register (DBB0ADDH) (Default Value:
0000_0000)
DBB0 address is according to {DBB0ADDH, DBB0ADDL}. Default I/O address is 0x00h.
If transmission is proceeding, address is encoded and decoded in next package.
6.2.1.4 Data Bus Buffer 0 Address Low Byte Register (DBB0ADDL) (Default Value:
0000_0000)
DBB0 address is according to {DBB0ADDH, DBB0ADDL}. Default I/O address is 0x00h.
If transmission is proceeding, address is encoded and decoded in next package.
6.2.1.5 Low Pin Count Control Register (LPCCON) (Default Value: 0000_0000)
Bit7: Data Bus Buffer 1 Enable
1: Enable (If transmission is proceeding, address is encoded and decoded in next package.)
0: Disable
Bit6: Data Bus Buffer 0 Enable
1: Enable (If transmission is proceeding, address is encoded and decoded in next package.)
0: Disable
Bit5: Serial IRQ 11 Enable
1: Enable (Start generating Serial IRQ for OBF1)
0: Disable (Stop generating Serial IRQ for OBF1)
Bit4: Serial IRQ 10 Enable
1: Enable (Start generating Serial IRQ for OBF1)
0: Disable (Stop generating Serial IRQ for OBF1)
Bit3: Serial IRQ 01 Enable
1: Enable (Start generating Serial IRQ for OBF0)
0: Disable (Stop generating Serial IRQ for OBF0)
Bit2: Serial IRQ 00 Enable
1: Enable (Start generating Serial IRQ for OBF0)
0: Disable (Stop generating Serial IRQ for OBF0)
Bit1: Serial IRQ 1 Generate Start Bit
W83L951DG/FG hardware checks this bit in every starting of Serial IRQ procedure. If this bit is high,
W83L951DG/FG will generate Serial IRQ corresponding to OBF1 SIRQ Number @SIRQ. This bit
clears as low automatically after W83L951DG/FG receives request and enters Serial IRQ procedure.
This bit is set as high in writing this bit and data is written to Data Bus Buffer 1 Register.
This bit is to provide the method to generate Serial IRQ that is needless through writing to Data Bus
Buffer 1 Register.
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Publication Release Date: August 2006
Revision 1.0